NB4N527S
3.3V, 2.5Gb/s Dual
AnyLevel™ to LVDS
Receiver/Driver/Buffer/
Translator with Internal
Input Termination
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MARKING
DIAGRAM*
16
1
NB4N527S is a clock or data Receiver/Driver/Buffer/Translator
capable of translating AnyLevel
TM
input signal (LVPECL, CML,
HSTL, LVDS, or LVTTL/LVCMOS) to LVDS. Depending on the
distance, noise immunity of the system design, and transmission line
media, this device will receive, drive or translate data or clock signals
up to 2.5 Gb/s or 1.5 GHz, respectively.
The NB4N527S has a wide input common mode range of
GND + 50 mV to V
CC
−
50 mV combined with two 50
W
internal
termination resistors is ideal for translating differential or
single−ended data or clock signals to 350 mV typical LVDS output
levels without use of any additional external components (Figure 6).
The device is offered in a small 3 mm x 3 mm QFN−16 package.
NB4N527S is targeted for data, wireless and telecom applications as
well as high speed logic interface where jitter and package size are
main requirements. Application notes, models, and support
documentation are available on www.onsemi.com.
•
Maximum Input Clock Frequency up to 1.5 GHz
•
Maximum Input Data Rate up to 2.5 Gb/s (Figure 5)
•
470 ps Maximum Propagation Delay\
•
1 ps Maximum RMS Jitter
•
140 ps Maximum Rise/Fall Times
•
Single Power Supply; V
CC
= 3.3 V
$10%
•
Temperature Compensated TIA/EIA−644 Compliant LVDS Outputs
•
Internal 50
W
Termination Resistor per Input Pin
•
GND + 50 mV to V
CC
−
50 mV V
CMR
Range
•
These are Pb−Free Devices
1
QFN−16
MN SUFFIX
CASE 485G
NB4N
527S
ALYW
G
G
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
VTD0
D0
D0
VTD0
50
W*
Q0
50
W*
Q0
VTD1
VOLTAGE (130 mV/div)
D1
D1
Device DDJ = 10 ps
VTD1
50
W*
Q1
50
W*
Q1
Figure 1. Functional Block Diagram
*R
TIN
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
Figure 2. Typical Output Waveform at 2.488 Gb/s with
PRBS 2
23−1
(V
INPP
= 400 mV; Input Signal DDJ = 14 ps)
TIME (58 ps/div)
©
Semiconductor Components Industries, LLC, 2011
June, 2011
−
Rev. 5
1
Publication Order Number:
NB4N527S/D
NB4N527S
VTD0 D0
16
V
TD1
D1
D1
V
TD1
1
2
NB4N527S
3
4
5
GND
6
NC
7
NC
8
V
CC
15
D0 VTD0
14
13
12 Q0
11 Q0
10 Q1
9
Q1
Exposed Pad (EP)
Figure 3. Pin Configuration
(Top View)
Table 1. PIN DESCRIPTION
Pin
1
2
3
4
5
6, 7
8
9
10
11
12
13
14
15
16
EP
Name
VTD1
D1
D1
VTD1
GND
NC
V
CC
Q1
Q1
Q0
Q0
VTD0
D0
D0
VTD0
LVDS Output
LVDS Output
LVDS Output
LVDS Output
−
LVPECL, CML, LVDS,
LVCMOS, LVTTL, HSTL
LVPECL, CML, LVDS,
LVCMOS, LVTTL, HSTL
−
I/O
−
LVPECL, CML, LVDS,
LVCMOS, LVTTL, HSTL
LVPECL, CML, LVDS,
LVCMOS, LVTTL, HSTL
−
−
Description
Internal 50
W
termination pin for D1. (R
TIN
)
Noninverted differential clock/data D1 input (Note 1).
Inverted differential clock/data D1 input (Note 1).
Internal 50
W
termination pin for D1. (R
TIN
)
0 V. Ground.
No connect.
Positive Supply Voltage.
Inverted D1 output. Typically loaded with 100
W
receiver termination
resistor across differential pair.
Noninverted D1 output. Typically loaded with 100
W
receiver termination
resistor across differential pair.
Inverted D0 output. Typically loaded with 100
W
receiver termination
resistor across differential pair.
Noninverted D0 output. Typically loaded with 100
W
receiver termination
resistor across differential pair.
Internal 50
W
termination pin for D0.
Noninverted differential clock/data D0 input (Note 1).
Inverted differential clock/data D0 input (Note 1).
Internal 50
W
termination pin for D0.
Exposed pad. EP on the package bottom is thermally connected to the die
improved heat transfer out of package. The pad is not electrically connected
to the die, but is recommended to be soldered to GND on the PCB.
1. In the differential configuration when the input termination pins(VTD0/VTD0, VTD1/ VTD1) are connected to a common termination voltage
or left open, and if no signal is applied on D0/D0, D1/D1 input, then the device will be susceptible to self−oscillation.
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2
NB4N527S
Table 2. ATTRIBUTES
Characteristics
Moisture Sensitivity (Note 2)
Flammability Rating
ESD Protection
Oxygen Index: 28 to 34
Human Body Model
Machine Model
Charged Device Model
Value
Level 1
UL 94 V−0 @ 0.125 in
> 2 kV
> 200 V
> 1 kV
281
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
2. For additional information, see Application Note AND8003/D.
Table 3. MAXIMUM RATINGS
Symbol
V
CC
V
I
I
IN
I
OSC
Parameter
Positive Power Supply
Positive Input
Input Current Through R
T
(50
W
Resistor)
Output Short Circuit Current
Line−to−Line (Q to Q)
Line−to−End (Q or Q to GND)
Operating Temperature Range
Storage Temperature Range
Thermal Resistance (Junction−to−Ambient) (Note 3)
Thermal Resistance (Junction−to−Case)
Wave Solder
Pb
Pb−Free
0 lfpm
500 lfpm
1S2P (Note 3)
QFN−16
QFN−16
QFN−16
Condition 1
GND = 0 V
GND = 0 V
Static
Surge
Q or Q to GND
Q to Q
QFN−16
Continuous
Continuous
V
I
= V
CC
Condition 2
Rating
3.8
3.8
35
70
12
24
−40
to +85
−65
to +150
41.6
35.2
4.0
265
265
Unit
V
V
mA
mA
mA
°C
°C
°C/W
°C/W
°C/W
°C
T
A
T
stg
q
JA
q
JC
T
sol
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
3. JEDEC standard multilayer board
−
1S2P (1 signal, 2 power) with 8 filled thermal vias under exposed pad.
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3
NB4N527S
Table 4. DC CHARACTERISTICS, CLOCK INPUTS, LVDS OUTPUTS
V
CC
= 3.0 V to 3.6 V, GND = 0 V, T
A
=
−40°C
to +85°C
Symbol
I
CC
V
th
V
IH
V
IL
V
IHD
V
ILD
V
CMR
V
ID
R
TIN
V
OD
DV
OD
V
OS
DV
OS
V
OH
V
OL
Power Supply Current (Note 8)
Characteristic
Min
Typ
40
Max
53
Unit
mA
DIFFERENTIAL INPUTS DRIVEN SINGLE−ENDED
(Figures 11, 12, 16, and 18)
Input Threshold Reference Voltage Range (Note 7)
Single−ended Input HIGH Voltage
Single−ended Input LOW Voltage
GND +100
V
th
+ 100
GND
V
CC
−
100
V
CC
V
th
−
100
V
CC
V
CC
−
100
V
CC
−
50
V
CC
50
60
mV
mV
mV
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY
(Figures 7, 8, 9, 10, 17, and 19)
Differential Input HIGH Voltage
Differential Input LOW Voltage
Input Common Mode Range (Differential Configuration)
Differential Input Voltage (V
IHD
−
V
ILD
)
Internal Input Termination Resistor
100
GND
GND + 50
100
40
mV
mV
mV
mV
W
LVDS OUTPUTS
(Note 4)
Differential Output Voltage
Change in Magnitude of V
OD
for Complementary Output States (Note 9)
Offset Voltage (Figure 15)
Change in Magnitude of V
OS
for Complementary Output States (Note 9)
Output HIGH Voltage (Note 5)
Output LOW Voltage (Note 6)
900
250
0
1125
0
1
1425
1075
1
450
25
1375
25
1600
mV
mV
mV
mV
mV
mV
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. LVDS outputs require 100
W
receiver termination resistor between differential pair. See Figure 14.
5. V
OH
max = V
OS
max +
½
V
OD
max.
6. V
OL
max = V
OS
min
−
½
V
OD
max.
7. V
th
is applied to the complementary input when operating in single−ended mode.
8. Input termination pins open, Dx/Dx at the DC level within V
CMR
and output pins loaded with R
L
= 100
W
across differential.
9. Parameter guaranteed by design verification not tested in production.
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4
NB4N527S
Table 5. AC CHARACTERISTICS
V
CC
= 3.0 V to 3.6 V, GND = 0 V; (Note 10)
−40°C
Symbol
V
OUTPP
f
DATA
t
PLH
,
t
PHL
t
SKEW
Characteristic
Output Voltage Amplitude (@ V
INPPmin
)
(Figure 4)
Maximum Operating Data Rate
Differential Input to Differential Output
Propagation Delay
Duty Cycle Skew (Note 11)
Within Device Skew (Note 17)
Device−to−Device Skew (Note 15)
RMS Random Clock Jitter (Note 13)
Deterministic Jitter (Note 14)
Crosstalk Induced Jitter (Note 16)
V
INPP
t
r
t
f
f
in
= 1.0 GHz
f
in
= 1.5 GHz
f
DATA
= 622 Mb/s
f
DATA
= 1.5 Gb/s
f
DATA
= 2.488 Gb/s
100
Q, Q
60
100
f
in
≤
1.0 GHz
f
in
= 1.5 GHz
Min
220
200
1.5
270
Typ
350
300
2.5
370
8
5
30
0.5
0.5
6
7
10
20
470
45
25
100
1
1
20
20
25
40
V
CC
−
GND
140
100
60
100
Max
Min
220
200
1.5
270
25°C
Typ
350
300
2.5
370
8
5
30
0.5
0.5
6
7
10
20
470
45
25
100
1
1
20
20
25
40
V
CC
−
GND
140
100
60
100
Max
Min
220
200
1.5
270
85°C
Typ
350
300
2.5
370
8
5
30
0.5
0.5
6
7
10
20
470
45
25
100
1
1
20
20
25
40
V
CC
−
GND
140
Max
Unit
mV
Gb/s
ps
ps
t
JITTER
ps
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 12)
Output Rise/Fall Times @ 250 MHz
(20%
−
80%)
mV
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
10. Measured by forcing V
INPPmin
with 50% duty cycle clock source and V
CC
−
1400 mV offset. All loading with an external R
L
= 100
W
across
“D” and “D” of the receiver. Input edge rates 150 ps (20%−80%).
11. See Figure 13 differential measurement of t
skew
= |t
PLH
−
t
PHL
| for a nominal 50% differential clock input waveform @ 250 MHz.
12. Input voltage swing is a single−ended measurement operating in differential mode.
13. RMS jitter with 50% duty cycle input clock signal.
14. Deterministic jitter with input NRZ data at PRBS 2
23
−1
and K28.5.
15. Skew is measured between outputs under identical transition @ 250 MHz.
16. Crosstalk induced jitter is the additive deterministic jitter to channel one with channel two active both running at 622 Gb/s PRBS 2
23
−1
as
an asynchronous signals.
17. The worst case condition between Q0/Q0 and Q1/Q1 from either D0/D0 or D1/D1, when both outputs have the same transition.
400
OUTPUT VOLTAGE AMPLITUDE (mV)
350
300
250
200
150
100
50
0
85°C
25°C
−40°C
0
0.5
1
1.5
2
2.5
3
INPUT CLOCK FREQUENCY (GHz)
Figure 4. Output Voltage Amplitude (V
OUTPP
) versus
Input Clock Frequency (f
in
) and Temperature (@ V
CC
= 3.3 V)
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