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74VCX164245GX

产品描述Bus Transceivers Translating Transcvr LV 16Bit Dual Supply
产品类别逻辑    逻辑   
文件大小107KB,共10页
制造商Fairchild
官网地址http://www.fairchildsemi.com/
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74VCX164245GX概述

Bus Transceivers Translating Transcvr LV 16Bit Dual Supply

74VCX164245GX规格参数

参数名称属性值
是否Rohs认证不符合
厂商名称Fairchild
零件包装代码BGA
包装说明5.50 MM, PLASTIC, MO-205, FBGA-54
针数54
Reach Compliance Codecompliant
其他特性1.65V TO 2.7V SUPPLY FOR PORT A; 2.3V TO 3.6V SUPPLY FOR PORT B
控制类型COMMON CONTROL
计数方向BIDIRECTIONAL
系列ALVC/VCX/A
JESD-30 代码R-PBGA-B54
JESD-609代码e0
长度8 mm
负载电容(CL)30 pF
逻辑集成电路类型BUS TRANSCEIVER
最大I(ol)0.018 A
湿度敏感等级3
位数8
功能数量2
端口数量2
端子数量54
最高工作温度85 °C
最低工作温度-40 °C
输出特性3-STATE
输出极性TRUE
封装主体材料PLASTIC/EPOXY
封装代码LFBGA
封装等效代码BGA54,6X9,32
封装形状RECTANGULAR
封装形式GRID ARRAY, LOW PROFILE, FINE PITCH
包装方法TAPE AND REEL
峰值回流温度(摄氏度)260
电源1.8/2.5,2.5/3.3 V
Prop。Delay @ Nom-Sup5.8 ns
传播延迟(tpd)6.2 ns
认证状态Not Qualified
座面最大高度1.4 mm
最大供电电压 (Vsup)2.7 V
最小供电电压 (Vsup)1.65 V
标称供电电压 (Vsup)1.8 V
表面贴装YES
技术CMOS
温度等级INDUSTRIAL
端子面层Tin/Lead (Sn/Pb)
端子形式BALL
端子节距0.8 mm
端子位置BOTTOM
处于峰值回流温度下的最长时间NOT SPECIFIED
翻译1.8/2.5V&3.3V
宽度5.5 mm
Base Number Matches1

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74VCX164245 Low Voltage 16-Bit Dual Supply Translating Transceiver with 3-STATE Outputs
March 2000
Revised June 2005
74VCX164245
Low Voltage 16-Bit Dual Supply Translating Transceiver
with 3-STATE Outputs
General Description
The VCX164245 is a dual supply, 16-bit translating trans-
ceiver that is designed for two way asynchronous commu-
nication between busses at different supply voltages by
providing true signal translation. The supply rails consist of
V
CCB
, which is the higher potential rail operating at 2.3V to
3.6V and V
CCA
, which is the lower potential rail operating at
1.65V to 2.7V. (V
CCA
must be less than or equal to V
CCB
for proper device operation.) This dual supply design
allows for translation from 1.8V to 2.5V busses to busses at
a higher potential, up to 3.3V.
The Transmit/Receive (T/R) input determines the direction
of data flow. Transmit (active-HIGH) enables data from A
Ports to B Ports. Receive (active-LOW) enables data from
B Ports to A Ports. The Output Enable (OE) input, when
HIGH, disables both A and B Ports by placing them in a
High-Z condition. The A Port interfaces with the lower volt-
age bus (1.8V

2.5V). The B Port interfaces with the
higher voltage bus (2.7V

3.3V). Also the VCX164245 is
designed so that the control pins (T/R
n
, OE
n
) are supplied
by V
CCB
.
The 74VCX164245 is suitable for mixed voltage applica-
tions such as notebook computers using a 1.8V CPU and
3.3V peripheral components. It is fabricated with an
Advanced CMOS technology to achieve high speed opera-
tion while maintaining low CMOS power dissipation.
Features
s
Bidirectional interface between busses ranging from
1.65V to 3.6V
s
Supports Live Insertion and Withdrawal (Note 1)
s
Static Drive (I
OH
/I
OL
)
r
24 mA @ 3.0V V
CC
r
18 mA @ 2.3V V
CC
r
6 mA @ 1.65V V
CC
s
Uses proprietary noise/EMI reduction circuitry
s
Functionally compatible with 74 series 16245
s
Latchup performance exceeds 300 mA
s
ESD performance:
Human Body Model
!
2000V
Machine model
!
200V
s
Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA)
Note 1:
To ensure the high impedance state during power up or power
down, OE
n
should be tied to V
CCB
through a pull up resistor. The minimum
value of the resistor is determined by the current sourcing capability of the
driver.
Ordering Code:
Order Number
74VCX164245G
(Note 2)(Note 3)
74VCX164245MTD
(Note 3)
Package Number
BGA54A
MTD48
Package Description
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Note 2:
Ordering Code “G” indicates Trays.
Note 3:
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Diagram
© 2005 Fairchild Semiconductor Corporation
DS500159
www.fairchildsemi.com

 
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