INTEGRATED CIRCUITS
74LVT543
3.3V Octal latched transceiver with
dual enable (3-State)
Product specification
Supersedes data of 1994 May 20
IC23 Data Handbook
1998 Feb 19
Philips
Semiconductors
Philips Semiconductors
Product specification
3.3V Octal latched transceiver with dual enable
(3-State)
74LVT543
FEATURES
•
Combines 74LVT245 and 74LVT373 type functions in one device
•
8-bit octal transceiver with D-type latch
•
Back-to-back registers for storage
•
Separate controls for data flow in each direction
•
Output capability: +64mA/–32mA
•
TTL input and output switching levels
•
Input and output interface capability to systems at 5V supply
•
Bus-hold data inputs eliminate the need for external pull-up
resistors to hold unused inputs
DESCRIPTION
The 74LVT543 is a high-performance BiCMOS product designed for
V
CC
operation at 3.3V.
This device contains two sets of D-type latches for temporary
storage of data flowing in either direction. Separate Latch Enable
(LEAB, LEBA) and Output Enable (OEAB, OEBA) inputs are
provided for each register to permit independent control of data
transfer in either direction. The outputs are guaranteed to sink
64mA.
FUNCTIONAL DESCRIPTION
The 74LVT543 contains two sets of eight D–type latches, with
separate control pins for each set. Using data flow from A to B as an
example, when the A-to-B Enable (EAB) input and the A-to-B Latch
Enable (LEAB) input are Low the A-to-B path is transparent. A
subsequent Low-to-High transition of the LEAB signal puts the A
data into the latches where it is stored and the B outputs no longer
change with the A inputs. With EAB and OEAB both Low, the
3-State B output buffers are active and display the data present at
the outputs of the A latches.
Control of data flow from B to A is similar, but using the EBA, LEBA,
and OEBA inputs.
•
Live insertion/extraction permitted
•
No bus current loading when output is tied to 5V bus
•
Power-up 3-State
•
Power-up reset
•
Latch-up protection exceeds 500mA per JEDEC Std 17
•
ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model
QUICK REFERENCE DATA
SYMBOL
t
PLH
t
PHL
C
IN
C
I/O
I
CCZ
PARAMETER
Propagation delay
An to Bn or Bn to An
Input capacitance
I/O capacitance
Total supply current
CONDITIONS
T
amb
= 25°C; GND = 0V
C
L
= 50pF;
V
CC
= 3.3V
V
I
= 0V or 3.0V
Outputs disabled; V
I/O
= 0V or 3.0V
Outputs disabled; V
CC
= 3.6V
TYPICAL
2.3
3.0
4
10
0.13
UNIT
ns
pF
pF
mA
ORDERING INFORMATION
PACKAGES
24-Pin Plastic SOL
24-Pin Plastic SSOP Type II
24-Pin Plastic TSSOP Type I
TEMPERATURE RANGE
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
OUTSIDE NORTH AMERICA
74LVT543 D
74LVT543 DB
74LVT543 PW
NORTH AMERICA
74LVT543 D
74LVT543 DB
74LVT543PW DH
DWG NUMBER
SOT137-1
SOT340-1
SOT355-1
PIN CONFIGURATION
LEBA
OEBA
1
2
24 V
CC
23 EBA
22 B0
21 B1
20 B2
19 B3
18 B4
17 B5
16 B6
15 B7
14 LEAB
13 OEAB
LOGIC SYMBOL
3
4
5
6
7
8
9
10
A0 3
A1 4
A2
A3
5
6
A0 A1 A2 A3 A4 A5 A6 A7
11
23
14
1
EAB
EBA
LEAB
LEBA
B0 B1 B2 B3 B4 B5 B6 B7
OEAB
OEBA
13
2
A4 7
A5 8
A6
9
A7 10
EAB 11
GND 12
22 21 20 19 18 17 16 15
SV00027
SV00026
1998 Feb 19
2
853-1749 18988
Philips Semiconductors
Product specification
3.3V Octal latched transceiver with dual enable
(3-State)
74LVT543
LOGIC SYMBOL (IEEE/IEC)
LOGIC DIAGRAM
DETAIL A
D
Q
22
B0
2
23
1
13
11
14
1EN3
G1
IC5
ZEN4 (AB)
GZ.
ZC6
A0
3
LE
Q
D
LE
3
V3
6D
4
5
6
7
8
9
10
5D
2V
22
21
20
19
18
17
A1
A2
A3
A4
A5
A6
A7
4
5
6
7
8
9
10
DETAIL A X 7
21
20
19
18
17
16
15
B1
B2
B3
B4
B5
B6
B7
OEBA
16
15
EBA
LEBA
2
13
23
1
11
14
EAB
LEAB
OEAB
SV00028
SV00029
PIN DESCRIPTION
PIN NUMBER
14, 1
11, 23
13, 2
3, 4, 5, 6, 7, 8, 9, 10
22, 21, 20, 19, 18, 17, 16, 15
12
24
SYMBOL
LEAB / LEBA
EAB / EBA
OEAB / OEBA
A0 – A7
B0 – B7
GND
V
CC
FUNCTION
A to B / B to A Latch Enable input (active-Low)
A to B / B to A Enable input (active-Low)
A to B / B to A Output Enable input (active-Low)
Port A, 3-State outputs
Port B, 3-State outputs
Ground (0V)
Positive supply voltage
FUNCTION TABLE
INPUTS
OEXX
H
X
L
L
L
L
L
L
H =
h =
L =
l =
EXX
X
H
↑
↑
L
L
L
L
LEXX
X
X
L
L
↑
↑
L
L
An or Bn
X
X
h
l
h
l
H
L
X =
↑
=
NC=
Z =
OUTPUTS
Bn or An
Z
Z
Z
Z
H
L
H
L
Disabled
Disabled
Disabled + Latch
Latch + Display
Transparent
STATUS
L
L
H
X
High voltage level
High voltage level one set-up time prior to the Low-to-High
transition of LEXX or EXX (XX = AB or BA)
Low voltage level
Low voltage level one set-up time prior to the Low-to-High
transition of LEXX or EXX (XX = AB or BA)
3
NC
Hold
Don’t care
Low-to-High transition of LEXX or EXX (XX = AB or BA)
No change
High impedance or “off” state
1998 Feb 19
Philips Semiconductors
Product specification
3.3V Octal latched transceiver with dual enable
(3-State)
74LVT543
ABSOLUTE MAXIMUM RATINGS
1, 2
SYMBOL
V
CC
I
IK
V
I
I
OK
V
OUT
I
O
OUT
T
stg
PARAMETER
DC supply voltage
DC input diode current
DC input voltage
3
DC output diode current
DC output voltage
3
DC output current
Output in High state
Storage temperature range
–64
–65 to 150
°C
V
O
< 0
Output in Off or High state
Output in Low state
V
I
< 0
CONDITIONS
RATING
–0.5 to +4.6
–50
–0.5 to +7.0
–50
–0.5 to +7.0
128
mA
UNIT
V
mA
V
mA
V
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
V
CC
V
I
V
IH
V
IL
I
OH
I
O
OL
∆t/∆v
T
amb
DC supply voltage
Input voltage
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
Low-level output current; current duty cycle
≤
50%; f
≥
1kHz
Input transition rise or fall rate; outputs enabled
Operating free-air temperature range
–40
PARAMETER
MIN
2.7
0
2.0
0.8
–32
32
mA
64
10
+85
ns/V
°C
MAX
3.6
5.5
V
V
V
V
mA
UNIT
1998 Feb 19
4
Philips Semiconductors
Product specification
3.3V Octal latched transceiver with dual enable
(3-State)
74LVT543
DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Temp = -40°C to +85°C
MIN
V
IK
Input clamp voltage
V
CC
= 2.7V; I
IK
= –18mA
V
CC
= 2.7 to 3.6V; I
OH
= –100µA
V
OH
High-level output voltage
V
CC
= 2.7V; I
OH
= –8mA
V
CC
= 3.0V; I
OH
= –32mA
V
CC
= 2.7V; I
OL
= 100µA
V
CC
= 2.7V; I
OL
= 24mA
V
OL
Low-level output voltage
V
CC
= 3.0V; I
OL
= 16mA
V
CC
= 3.0V; I
OL
= 32mA
V
CC
= 3.0V; I
OL
= 64mA
V
RST
Power-up output low voltage
5
V
CC
= 3.6V; I
O
= 1mA; V
I
= GND or V
CC
V
CC
= 3.6V; V
I
= V
CC
or GND
V
CC
= 0 or 3.6V; V
I
= 5.5V
I
I
Input leakage current
V
CC
= 3.6V; V
I
= 5.5V
V
CC
= 3.6V; V
I
= V
CC
V
CC
= 3.6V; V
I
= 0
I
OFF
I
HOLD
Output off current
Bus Hold current A
inputs
6
V
CC
= 0V; V
I
or V
O
= 0 to 4.5V
V
CC
= 3V; V
I
= 0.8V
V
CC
= 3V; V
I
= 2.0V
V
CC
= 0V to 3.6V; V
CC
= 3.6V
I
EX
I
PU/PD
I
CCH
I
CCL
I
CCZ
∆I
CC
Additional supply current per
input pin
2
Quiescent supply current
Current into an output in the
High state when V
O
> V
CC
Power up/down 3-State output
current
3
V
O
= 5.5V; V
CC
= 3.0V
V
CC
≤
1.2V; V
O
= 0.5V to V
CC
; V
I
= GND or V
CC
;
OE/OE = Don’t care
V
CC
= 3.6V; Outputs High, V
I
= GND or V
CC,
I
O =
0
V
CC
= 3.6V; Outputs Low, V
I
= GND or V
CC,
I
O =
0
V
CC
= 3.6V; Outputs Disabled; V
I
= GND or V
CC,
I
O =
0
V
CC
= 3V to 3.6V; One input at V
CC
-0.6V,
Other inputs at V
CC
or GND
75
–75
±500
60
15
0.13
3
0.13
0.1
125
±100
0.19
12
0.19
0.2
mA
mA
µA
µA
I/O Data pins
4
Control pins
V
CC
-0.2
2.4
2.0
TYP
1
–0.9
V
CC
-0.1
2.5
2.2
0.1
0.3
0.25
0.3
0.4
0.13
±0.1
1
1
0.1
–1
1
150
–150
µA
0.2
0.5
0.4
0.5
0.55
0.55
±1
10
20
1
-5
±100
µA
µA
V
V
V
MAX
–1.2
V
UNIT
NOTES:
1. All typical values are at V
CC
= 3.3V and T
amb
= 25°C.
2. This is the increase in supply current for each input at the specified voltage level other than V
CC
or GND
3. This parameter is valid for any V
CC
between 0V and 1.2V with a transition time of up to 10msec. From V
CC
= 1.2V to V
CC
= 3.3V
±
0.3V a
transition time of 100µsec is permitted. This parameter is valid for T
amb
= 25°C only.
4. Unused pins at V
CC
or GND.
5. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.
6. This is the bus hold overdrive current required to force the input to the opposite logic state.
1998 Feb 19
5
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