NTP18N06L, NTB18N06L
Power MOSFET
15 Amps, 60 Volts,
Logic Level
N−Channel TO−220 and D
2
PAK
Designed for low voltage, high speed switching applications in
power supplies, converters and power motor controls and bridge
circuits.
Features
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15 AMPERES, 60 VOLTS
R
DS(on)
= 100 mW
N−Channel
D
•
Pb−Free Packages are Available
Typical Applications
•
•
•
•
Power Supplies
Converters
Power Motor Controls
Bridge Circuits
G
S
4
Value
60
60
"10
"20
15
8.0
45
48.4
0.32
−55 to
+175
61
Adc
Adc
A
pk
W
W/°C
°C
mJ
NTx18N06LG
AYWW
°C/W
R
qJC
R
qJA
T
L
3.1
72.5
260
°C
1
Gate
2
Drain
3
Source
1
Gate
Unit
Vdc
Vdc
Vdc
1
TO−220AB
CASE 221A
STYLE 5
2
3
1
2
3
D
2
PAK
CASE 418AA
STYLE 2
4
MAXIMUM RATINGS
(T
J
= 25°C unless otherwise noted)
Rating
Drain−to−Source Voltage
Drain−to−Gate Voltage (R
GS
= 10 mW)
Gate−to−Source Voltage
− Continuous
− Non−Repetitive (t
p
v
10 ms)
Drain Current
− Continuous @ T
C
= 25°C
− Continuous @ T
C
= 100°C
− Single Pulse (t
p
v
10
ms)
Total Power Dissipation @ T
C
= 25°C
Derate above 25°C
Operating and Storage Temperature Range
Single Pulse Drain−to−Source Avalanche
Energy − Starting T
J
= 25°C
(V
DD
= 25 Vdc, V
GS
= 5.0 Vdc, V
DS
= 60 Vdc,
I
L(pk)
= 11 A, L = 1.0 mH, R
G
= 25
W)
Thermal Resistance
− Junction−to−Case
− Junction−to−Ambient
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from case for 10 seconds
Symbol
V
DSS
V
DGR
V
GS
I
D
I
D
I
DM
P
D
T
J
, T
stg
E
AS
MARKING DIAGRAMS
& PIN ASSIGNMENTS
4
Drain
4
Drain
NTx
18N06LG
AYWW
3
Source
2
Drain
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
NTx18N06L
x
A
Y
WW
G
= Device Code
= B or P
= Assembly Location
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
©
Semiconductor Components Industries, LLC, 2005
1
August, 2005 − Rev. 4
Publication Order Number:
NTP18N06L/D
NTP18N06L, NTB18N06L
ELECTRICAL CHARACTERISTICS
(T
J
= 25°C unless otherwise noted)
Characteristic
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage (Note 1)
(V
GS
= 0 Vdc, I
D
= 250
mAdc)
Temperature Coefficient (Positive)
Zero Gate Voltage Drain Current
(V
GS
= 0 Vdc, V
DS
= 60 Vdc)
(V
GS
= 0 Vdc, V
DS
= 60 Vdc, T
J
= 150°C)
Gate−Body Leakage Current (V
GS
=
±
15 Vdc, V
DS
= 0 Vdc)
ON CHARACTERISTICS
(Note 1)
Gate Threshold Voltage (Note 1)
(V
DS
= V
GS,
I
D
= 250
mAdc)
Threshold Temperature Coefficient (Negative)
Static Drain−to−Source On−Resistance (Note 1)
(V
GS
= 5.0 Vdc, I
D
= 7.5 Adc)
Static Drain−to−Source On−Voltage (Note 1)
(V
GS
= 5.0 Vdc, I
D
= 15 Adc)
(V
GS
= 5.0 Vdc, I
D
= 7.5 Adc, T
J
= 150°C)
Forward Transconductance (Note 1) (V
DS
= 7.0 Vdc, I
D
= 6.0 Adc)
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS
(Note 2)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
Gate Charge
(V
DD
= 30 Vdc, I
D
= 15 Adc,
V
GS
= 5.0 Vdc,
R
G
= 9.1
W)
(Note 1)
(V
DS
= 48 Vdc, I
D
= 15 Adc,
V
GS
= 5.0 Vdc) (Note 1)
SOURCE−DRAIN DIODE CHARACTERISTICS
Diode Forward On−Voltage
Reverse Recovery Time
(I
S
= 15 Adc, V
GS
= 0 Vdc,
dI
S
/dt = 100 A/ms) (Note 1)
(I
S
= 15 Adc, V
GS
= 0 Vdc) (Note 1)
(I
S
= 15 Adc, V
GS
= 0 Vdc, T
J
= 150°C)
V
SD
t
rr
t
a
t
b
Q
RR
−
−
−
−
−
−
0.96
0.83
35
23
12
0.043
1.2
−
−
−
−
−
mC
Vdc
ns
t
d(on)
t
r
t
d(off)
t
f
Q
t
Q
1
Q
2
−
−
−
−
−
−
−
11
121
11
42
7.3
1.9
4.3
20
210
40
80
20
−
−
nC
ns
(V
DS
= 25 Vdc, V
GS
= 0 Vdc,
f = 1.0 MHz)
C
iss
C
oss
C
rss
−
−
−
310
106
37
440
150
70
pF
V
GS(th)
1.0
−
R
DS(on)
−
V
DS(on)
−
−
g
FS
−
1.46
1.2
9.4
1.8
−
−
mhos
85
100
Vdc
1.6
4.2
2.0
−
Vdc
mV/°C
mW
V
(BR)DSS
60
−
I
DSS
−
−
I
GSS
−
−
−
−
1.0
10
±
100
nAdc
70
63.2
−
−
Vdc
mV/°C
mAdc
Symbol
Min
Typ
Max
Unit
Reverse Recovery Stored
Charge
1. Pulse Test: Pulse Width = 300
ms,
Duty Cycle = 2%.
2. Switching characteristics are independent of operating junction temperature.
ORDERING INFORMATION
Device
NTP18N06L
NTP18N06LG
NTB18N06L
NTB18N06LG
NTB18N06LT4
NTB18N06LT4G
Package
TO−220AB
TO−220AB
(Pb−Free)
D
2
PAK
D
2
PAK
(Pb−Free)
D
2
PAK
D
2
PAK
(Pb−Free)
Shipping
†
50 Units/Rail
50 Units/Rail
50 Units/Rail
50 Units/Rail
800/Tape & Reel
800/Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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2
NTP18N06L, NTB18N06L
32
V
GS
= 10 V
I
D
, DRAIN CURRENT (AMPS)
24
8V
6V
5V
4.5 V
16
4V
8
3.5 V
3V
0
0
2
4
6
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
8
I
D
, DRAIN CURRENT (AMPS)
32
V
DS
≥
10 V
24
16
8
T
J
= 25°C
T
J
= 100°C
T
J
= −55°C
7
0
1
2
3
4
5
6
V
GS
, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 1. On−Region Characteristics
R
DS(on)
, DRAIN−TO−SOURCE RESISTANCE (W)
R
DS(on)
, DRAIN−TO−SOURCE RESISTANCE (W)
Figure 2. Transfer Characteristics
0.32
V
GS
= 5 V
0.24
T
J
= 100°C
0.16
T
J
= 25°C
0.08
T
J
= −55°C
0.32
V
GS
= 10 V
0.24
0.16
T
J
= 100°C
T
J
= 25°C
0.08
T
J
= −55°C
0
0
8
16
24
I
D
, DRAIN CURRENT (AMPS)
32
0
0
8
16
24
I
D
, DRAIN CURRENT (AMPS)
32
R
DS(on),
DRAIN−TO−SOURCE RESISTANCE (NORMALIZED)
Figure 3. On−Resistance versus
Gate−to−Source Voltage
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
2
1.8
1.6
1.4
1.2
1
0.8
0.6
−50 −25
0
25
50
75 100 125 150
T
J
, JUNCTION TEMPERATURE (°C)
175
I
D
= 7.5 A
V
GS
= 5 V
10,000
V
GS
= 0 V
T
J
= 150°C
I
DSS
, LEAKAGE (nA)
1000
100
T
J
= 100°C
10
1
0
10
20
30
40
50
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
60
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
versus Voltage
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NTP18N06L, NTB18N06L
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Dt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (I
G(AV)
) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/I
G(AV)
During the rise and fall time interval when switching a
resistive load, V
GS
remains virtually constant at a level
known as the plateau voltage, V
SGP
. Therefore, rise and fall
times may be approximated by the following:
t
r
= Q
2
x R
G
/(V
GG
− V
GSP
)
t
f
= Q
2
x R
G
/V
GSP
where
V
GG
= the gate drive voltage, which varies from zero to V
GG
R
G
= the gate drive resistance
and Q
2
and V
GSP
are read from the gate charge curve.
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
t
d(on)
= R
G
C
iss
In [V
GG
/(V
GG
− V
GSP
)]
t
d(off)
= R
G
C
iss
In (V
GG
/V
GSP
)
The capacitance (C
iss
) is read from the capacitance curve at
a voltage corresponding to the off−state condition when
calculating t
d(on)
and is read at a voltage corresponding to the
on−state when calculating t
d(off)
.
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
1200
1000
C, CAPACITANCE (pF)
V
DS
= 0 V V
GS
= 0 V
C
iss
T
J
= 25°C
800
600
400
200
0
10
5
V
GS
0
V
DS
C
rss
5
10
15
20
25
C
rss
C
iss
C
oss
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
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4
NTP18N06L, NTB18N06L
VGS , GATE−TO−SOURCE VOLTAGE (VOLTS)
6
Q
T
Q
1
4
Q
2
t, TIME (ns)
100
1000
V
DS
= 30 V
I
D
= 15 A
V
GS
= 5 V
t
r
t
f
10
I
D
= 15 A
T
J
= 25°C
0
0
2
4
6
Q
G
, TOTAL GATE CHARGE (nC)
8
1
1
10
R
G
, GATE RESISTANCE (W)
100
t
d(off)
t
d(on)
V
GS
2
Figure 8. Gate−To−Source and Drain−To−Source
Voltage versus Total Charge
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
16
IS, SOURCE CURRENT (AMPS)
V
GS
= 0 V
12
8
4
T
J
= 150°C
T
J
= 25°C
0
0.3
0.8
0.9
0.6
0.7
V
SD
, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
0.4
0.5
1
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
reliable operation, the stored energy from circuit inductance
The Forward Biased Safe Operating Area curves define
dissipated in the transistor while in avalanche must be less
the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
than the rated limit and adjusted for operating conditions
forward biased. Curves are based upon maximum peak
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
junction temperature and a case temperature (T
C
) of 25°C.
Peak repetitive pulsed power limits are determined by using
a constant. The energy rating decreases non−linearly with an
the thermal response data in conjunction with the procedures
increase of peak current in avalanche and peak junction
discussed in AN569, “Transient Thermal Resistance −
temperature.
General Data and Its Use.”
Although many E−FETs can withstand the stress of
Switching between the off−state and the on−state may
drain−to−source avalanche at currents up to rated pulsed
current (I
DM
), the energy rating is specified at rated
traverse any load line provided neither rated peak current
(I
DM
) nor rated voltage (V
DSS
) is exceeded and the
continuous current (I
D
), in accordance with industry custom.
The energy rating must be derated for temperature as shown
transition time (t
r
,t
f
) do not exceed 10
ms.
In addition the total
in the accompanying graph (Figure 12). Maximum energy at
power averaged over a complete switching cycle must not
currents below rated continuous I
D
can safely be assumed to
exceed (T
J(MAX)
− T
C
)/(R
qJC
).
equal the values indicated.
A Power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For
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