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74LVC823A
9-bit D-type flip-flop with 5 V tolerant inputs/outputs; positive
edge-trigger; 3-state
Rev. 4 — 8 April 2013
Product data sheet
1. General description
The 74LVC823A is a 9-bit D-type flip-flop with common clock (pin CP), clock enable
(pin CE), master reset (pin MR) and 3-state outputs (pins Qn) for bus-oriented
applications. The 9 flip-flops stores the state of their individual D-inputs that meet the
set-up and hold times requirements on the LOW to HIGH CP transition, provided pin CE is
LOW. When pin CE is HIGH, the flip-flops hold their data. A LOW on pin MR resets all
flip-flops. When pin OE is LOW, the contents of the 9 flip-flops are available at the outputs.
When pin OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the
OE input does not affect the state of the flip-flops.
Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be
applied to the outputs. These features allow the use of these devices as translators in
mixed 3.3 V and 5 V applications.
2. Features and benefits
5 V tolerant inputs/outputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
Direct interface with TTL levels
Flow-through pinout architecture
9-bit positive edge-triggered register
Independent register and 3-state buffer operation
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-B exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Specified from
40 C
to +85
C
and
40 C
to +125
C.
NXP Semiconductors
74LVC823A
9-bit D-type flip-flop; 5 V tolerance; positive edge-trigger; 3-state
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74LVC823AD
74LVC823ADB
74LVC823APW
74LVC823ABQ
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
Name
SO24
SSOP24
TSSOP24
DHVQFN24
Description
plastic small outline package; 24 leads;
body width 7.5 mm
plastic shrink small outline package; 24 leads;
body width 5.3 mm
plastic thin shrink small outline package; 24 leads;
body width 4.4 mm
Version
SOT137-1
SOT340-1
SOT355-1
Type number
plastic dual in-line compatible thermal enhanced very SOT815-1
thin quad flat package; no leads; 24 terminals;
body 3.5
5.5
0.85 mm
4. Functional diagram
2
3
4
5
6
7
8
9
10
D0
D1
D2
D3
D4
D5
D6
D7
D8
Q0
Q1
Q2
Q3
23
22
21
20
19
18
17
16
15
FF0
to
FF8
3-STATE
OUTPUTS
Q4
Q5
Q6
Q7
Q8
13
11
14
1
CP
MR
CE
OE
001aaa849
Fig 1.
Functional diagram
74LVC823A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 4 — 8 April 2013
2 of 21
NXP Semiconductors
74LVC823A
9-bit D-type flip-flop; 5 V tolerance; positive edge-trigger; 3-state
1
11
14
11
2
3
4
5
6
7
8
9
10
MR
D0
D1
D2
D3
D4
D5
D6
D7
D8
CP
13
1
OE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
CE
14
001aaa847
EN
R
G1
1C2
23
22
21
20
19
18
17
16
15
001aaa848
13
23
22
21
20
19
18
17
16
15
2
3
4
5
6
7
8
9
10
2D
Fig 2.
Logic symbol
Fig 3.
IEC logic symbol
74LVC823A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 4 — 8 April 2013
3 of 21
NXP Semiconductors
74LVC823A
9-bit D-type flip-flop; 5 V tolerance; positive edge-trigger; 3-state
D0
D1
D2
D3
D4
MR
R
R
R
R
R
CE
D
Q
D
Q
D
Q
D
Q
D
Q
CP
FF0
CP
FF1
CP
FF2
CP
FF3
CP
FF4
CP
OE
Q0
D5
D6
Q1
D7
Q2
D8
Q3
Q4
D
R
Q
D
R
Q
D
R
Q
D
R
Q
CP
FF5
CP
FF6
CP
FF7
CP
FF8
Q5
Q6
Q7
Q8
001aaa850
Fig 4.
Logic diagram
74LVC823A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 4 — 8 April 2013
4 of 21
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