IR213(6,62,63,65,66,67,68)(J&S) & PbF
Data Sheet No. PD60166 revU
IR2136/IR21362/IR21363/IR21365/
IR21366/IR21367/IR21368 (J&S) & (PbF)
3-PHASE BRIDGE DRIVER
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Floating channel designed for bootstrap operation
Fully operational to +600 V
Tolerant to negative transient voltage, dV/dt immune
Gate drive supply range from 10 V to 20 V (IR2136/
IR21368), 11.5 V to 20 V (IR21362D), or 12 V to 20 V
(IR21363/IR21365/IR21366/IR21367)
Undervoltage lockout for all channels
Over-current shutdown turns off all six drivers
Independent 3 half-bridge drivers
Matched propagation delay for all channels
Cross-conduction prevention logic
Low side output out of phase with inputs. High side outputs
out of phase (IR213(6,63, 65, 66, 67, 68)), or in phase
(IR21362) with inputs
3.3 V logic compatible
Lower di/dt gate drive for better noise immunity
Externally programmable delay for automatic fault clear
All parts are LEAD-FREE
Packages
28-Lead SOIC
28-Lead PDIP
44-Lead PLCC w/o 12 Leads
Description
Feature Comparison:
IR213(6,62,63,65,66,67,68)
Part
IR2136
IR21362
IR21363
IR21365
IR21366
IR21367
IR21368
The IR2136x (J&S) are high voltage, high
___ ___
___
___ ___
___ ___
___ ___
___ ___
___ ___
Input Logic
speed power MOSFET and IGBT drivers with
HIN, LIN
HIN, LIN
HIN, LIN
HIN, LIN
HIN, LIN
HIN, LIN
HIN, LIN
three independent high and low side
Ton (typ.)
400 ns
400 ns
400 ns
400 ns
250 ns
250 ns
400 ns
referenced output channels for 3-phase
Toff (typ.)
380ns
380 ns
380 ns
380 ns
180 ns
180 ns
380 ns
applications. Proprietary HVIC technology
V (typ.)
2.7 V
2.7 V
2.7 V
2.7 V
2.0 V
2.0 V
2.0 V
V (typ.)
1.7 V
1.7 V
1.7 V
1.7 V
1.3 V
1.3 V
1.3 V
enables ruggedized monolithic construction.
Vitrip+
0.46 V
0.46 V
0.46 V
4.3 V
0.46 V
4.3 V
4.3 V
Logic inputs are compatible with CMOS or
UVCC/BS+
8.9 V
10.4 V
11.2 V
11.2 V
11.2 V
11.2 V
8.9 V
LSTTL outputs, down to 3.3 V logic. A current
UVCC/BS-
8.2 V
9.4 V
11.0 V
11.0 V
11.0 V
11.0 V
8.2 V
trip function which terminates all six outputs
can be derived from an external current sense resistor. An enable function is available to terminate all six outputs simultaneously. An
open-drain FAULT signal is provided to indicate that an overcurrent or undervoltage shutdown has occurred. Overcurrent fault
conditions are cleared automatically after a delay programmed externally via an RC network connected to the RCIN input. The output
drivers feature a high pulse current buffer stage designed for minimum driver cross-conduction. Propagation delays are matched to
simplify use in high frequency applications. The floating channels can be used to drive N-channel power MOSFETs or IGBTs in the
high side configuration which operates up to 600 V.
IH
IL
Typical Connection
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1
IR213(6,62,63,65,66,67,68)(J&S) & PbF
Absolute Maximum Ratings
Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage
parameters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are
measured under board mounted and still air conditions.
Symbol
V
S
V
B
V
HO
V
CC
V
SS
V
LO1,2,3
V
IN
V
RCIN
V
FLT
dV/dt
P
D
Definition
High side offset voltage
High side floating supply voltage
High side floating output voltage
Low side and logic fixed supply voltage
Logic ground
Low side output voltage
Input voltage LIN, HIN, ITRIP, EN
RCIN input voltage
FAULT output voltage
Allowable offset voltage slew rate
Package power dissipation
@ T
A
≤
+25 °C
Thermal resistance, junction to
ambient
Junction temperature
Storage temperature
Lead temperature (soldering, 10 seconds)
(28 lead PDIP)
(28 lead SOIC)
(44 lead PLCC)
(28 lead PDIP)
(28 lead SOIC)
(44 lead PLCC)
Min
V
B 1,2,3
- 25
-0.3
-0.3
V
CC
- 25
-0.3
V
SS
-0.3
V
SS
-0.3
V
SS
-0.3
—
—
—
—
—
—
—
—
-55
—
Max
V
B 1,2,3
+ 0.3
625
25
V
CC
+ 0.3
V
CC
+ 0.3
Lower of
(V
SS
+ 15) or
V
CC
+ 0.3)
V
CC
+ 0.3
V
CC
+ 0.3
50
1.5
1.6
2.0
83
78
63
150
150
300
Units
V
S1,2,3
- 0.3 V
B 1,2,3
+ 0.3
V
V/ns
W
Rth
JA
T
J
T
S
T
L
°C/W
°C
Recommended Operating Conditions
The input/output logic-timing diagram is shown in Fig. 1. For proper operation the device should be used within the
recommended conditions. All voltage parameters are absolute referenced to COM. The V
S
offset ratings are tested
with all supplies biased at a 15 V differential.
Symbol
V
B1,2,3
V
S 1,2,3
V
HO 1,2,3
V
LO1,2,3
V
CC
V
SS
V
FLT
Definition
IR213(6,68)
High side floating supply voltage IR21362
High side floating supply offset voltage
High side output voltage
Low side output voltage
Low side and logic fixed supply
IR21362
voltage
IR213(6,63,65,66,67)
Logic ground
FAULT output voltage
IR213(6,68)
Min
V
S1,2,3
+10
V
S1,2,3
+11.5
Note 1
V
S1,2,3
0
10
11.5
12
-5
V
SS
Max
V
S1,2,3
+ 20
V
S1,2,3
+ 20
V
S1,2,3
+ 20
600
V
B1,2,3
V
CC
20
20
20
5
V
CC
Units
IR213(6,63,65,66,67) V
S1,2,3
+12
V
V
RCIN
RCIN input voltage
V
SS
V
CC
Note 1:
Logic operational for V
S
of (COM - 5 V) to (COM + 600 V). Logic state held for V
S
of (COM - 5 V) to (COM – V
BS
).
(Please refer to the Design Tip DT97-3 for more details).
Note 2:
All input pins and the ITRIP and EN pins are internally clamped with a 5.2 V zener diode.
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IR213(6,62,63,65,66,67,68)(J&S) & PbF
Recommended Operating Conditions - (Continued)
The input/output logic-timing diagram is shown in Fig. 1. For proper operation the device should be used within the
recommended conditions. All voltage parameters are absolute referenced to COM. The V
S
offset ratings are tested
with all supplies biased at a 15 V differential.
Symbol
V
ITRIP
Definition
Min
Max
V
SS
+ 5
V
SS
+ 5
125
Units
V
°C
ITRIP input voltage
V
SS
Logic input voltage LIN, HIN (IR213(6,63,65,66,67,68)),
V
IN
V
SS
HIN (IR21362), EN
T
A
Ambient temperature
-40
Note 2:
All input pins and the ITRIP and EN pins are internally clamped with a 5.2 V zener diode.
Static Electrical Characteristics
V
BIAS
(V
CC
,V
BS1,2,3
) = 15 V unless otherwise specified. The V
IN
, V
TH
, and I
IN
parameters are referenced to V
SS
and are
applicable to all six channels (HIN1,2,3 and LIN1,2,3). The V
O
and I
O
parameters are referenced to COM and V
S1,2,3
and are applicable to the respective output leads: HO1,2,3 and LO1,2,3.
Symbol
Definition
Min Typ Max Units Test Conditions
Logic “0” input voltage LIN1,2,3, HIN1,2,3
IR213(6,63,65)
3.0
—
—
V
IH
Logic “1” input voltage HIN1,2,3 IR21362
Logic “0” input voltage LIN1,2,3, HIN1,2,3
2.5
—
—
IR213(66,67,68)
Logic “1” input Voltage LIN1,2,3, HIN1,2,3
IR213(6,63,65)
Logic “0” input voltage HIN1,2,3 IR21362
V
IL
—
—
0.8
Logic “0” input voltage LIN1,2,3, HIN1,2,3
IR213(66,67,68)
V
EN,TH+
Enable positive going threshold
—
—
3
V
EN,TH-
V
IT,TH+
V
IT,HYS
V
RCIN, TH+
V
RCIN, HYS
V
OH
V
OL
V
CCUV+
V
BSUV+
Enable negative going threshold
ITRIP positive going
threshold
ITRIP input hysteresis
RCIN positive going threshold
RCIN input hysteresis
High level output voltage, V
BIAS
- V
O
Low level output voltage, V
O
V
CC
and V
BS
supply
undervoltage positive going
threshold
IR2136(2)(3)(6)
IR21365(7)(8)
IR2136(2)(3)(6)
IR21365(7)(8)
0.8
—
—
0.55
4.75
—
—
—
—
1.4
0.6
9.8
11.2
11.6
Io = 20 mA
V
0.37 0.46
3.85 4.30
—
—
—
—
—
0.07
.15
8
3
0.9
—
0.4
IR2136(8)
8.0 8.9
IR21362
9.6 10.4
IR21363(5)(6)(7) 10.6 11.1
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IR213(6,62,63,65,66,67,68)(J&S) & PbF
Static Electrical Characteristics - (Continued)
V
BIAS
(V
CC
,V
BS1,2,3
) = 15 V unless otherwise specified. The V
IN
, V
TH
, and I
IN
parameters are referenced to V
SS
and are
applicable to all six channels (HIN1,2,3 and LIN1,2,3). The V
O
and I
O
parameters are referenced to COM and V
S1,2,3
and
are applicable to the respective output leads: HO1,2,3 and LO1,2,3.
Symbol
V
CCUV-
V
BSUV-
V
CCUVH
V
BSUVH
I
LK
I
QBS
I
QCC
V
IN,CLAMP
I
LIN+
I
LIN-
I
HIN+
I
HIN-
I
ITRIP+
I
ITRIP-
I
EN+
I
EN-
I
RCIN
I
O+
I
O-
R
on_RCIN
R
on_FAULT
Definition
V
CC
and V
BS
supply
undervoltage negative going
threshold
V
CC
and V
BS
supply
undervoltage lockout
hysteresis
Offset supply leakage current
Quiescent V
BS
supply current
Quiescent V
CC
supply current
IR2136(8)
IR21362
IR2136(3,5,6,7)
IR2136
IR21362
IR2136(3,5)
Min Typ Max Units Test Conditions
7.4 8.2
8.6 9.4
10.4 10.9
0.3 0.7
0.5
—
—
—
—
1.0
0.2
—
70
1.6
5.2
200
30
100
0
200
30
30
100
0
30
0
30
0
0
200
350
50
50
9.0
10.2
11.4
—
—
—
50
120
2.3
5.5
300
100
220
1
300
100
100
220
1
100
1
100
1
1
—
mA
—
100
100
Ω
mA
V
µA
V
B1,2,3
= V
S1,2,3
=
600 V
V
IN
= 0 V or 5 V
I
IN
=100 µA
V
LIN
= 5 V
V
LIN
= 0 V
V
HIN
= 5 V
µA
V
HIN
= 0 V
V
ITRIP
= 5 V
V
ITRIP
= 0 V
V
ENABLE
= 5 V
V
ENABLE
=0 V
Vrcin= 0 V or
15 V
Vo =0 V,
PW
≤10
µs
Vo =15 V,
PW
≤10
µs
V
Input clamp voltage (HIN, LIN, ITRIP and EN)
4.9
IR2136(2,3,5)
—
Input bias current (LOUT = HI)
IR2136(6,7,8)
—
IR2136(2,3,5)
—
Input bias current (LOUT = LO)
IR2136(6,7,8)
—
IR2136(3,5)
—
Input bias current (HOUT = HI) IR21362
—
IR2136(6,7,8)
—
IR2136(3,5)
—
Input bias current (HOUT = LO)
IR2136(2,6,7,8) —
“High” ITRIP input bias current
—
“Low” ITRIP input bias current
“High” ENABLE input bias current
“Low” ENABLE input bias current
RCIN input bias current
Output high short circuit pulsed current
Output low short circuit pulsed current
RCIN low on resistance
FAULT low on resistance
—
—
—
—
120
250
—
—
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IR213(6,62,63,65,66,67,68)(J&S) & PbF
Dynamic Electrical Characteristics
V
CC
= V
BS
= V
BIAS
= 15 V, V
S1,2,3
= V
SS
= COM, T
A
= 25 °C and CL = 1000 pF unless otherwise specified.
Symbol
t
on
t
off
t
r
t
f
t
EN
t
ITRIP
t
bl
t
FLT
t
FILIN
t
FLTCLR
DT
MT
Definition
Turn-on propagation delay
Turn-off propagation delay
Turn-on rise time
Turn-off fall time
ENABLE low to output shutdown
propagation delay
IR2136(6,7)
Min Typ Max Units
IR2136(2,3,5,8) 300
IR2136(6,7)
—
IR2136(2,3,5,8) 250
IR2136(6,7)
—
—
—
IR2136(2,3,5,8) 300
100
500
100
400
100
1.3
220
—
—
—
425
250
400
180
125
50
450
250
750
150
600
200
1.65
290
40
25
40
550
—
550
—
190
75
600
400
1000
—
800
—
2
360
75
70
75
ns
ms
ns
Test
Conditions
V
IN
= 0 V & 5 V
V
IN,
V
EN
= 0 V
or 5 V
V
ITRIP
= 5 V
V
IN
= 0 V or 5 V
V
ITRIP
= 5 V
V
IN
= 0 V & 5 V
V
IN
= 0 V or 5 V
V
ITRIP
= 0 V
V
IN
= 0 V & 5 V
External dead
time >400 ns
ITRIP to output shutdown propagation delay
ITRIP blanking time
ITRIP to FAULT propagation delay
Input filter time (HIN, LIN)
(IR213(6,62,63,65,68) only)
FAULT clear time RCIN: R = 2 MΩ, C = 1 nF
Deadtime
Matching delay ON and OFF
Matching delay, max (t
on
, t
off
) – min (t
on
, t
off
),
MDT
(t
on
, t
off
are applicable to all 3 channels)
PM
Output pulse width matching (pwin-pwout) (Fig.2)
Note:
For high side PWM, HIN pulse width must be
≥
1 µs.
VCC
VBS
ITRIP
ENABLE
FAULT
LO1,2,3
HO1,2,3
<UVCC
X
X
X
0 (note 1)
0
0
15 V
<UVBS
0V
5V
high imp
LIN1,2,3
0
15 V
15 V
0V
5V
high imp
LIN1,2,3
HIN1,2,3
15 V
15 V
>V
ITRIP
5V
0 (note 2)
0
0
15 V
15 V
0V
0V
high imp
0
0
Note 1:
A shoot-through prevention logic prevents LO1,2,3 and HO1,2,3 for each channel from turning on simultaneously.
Note 2:
UVCC is not latched, when V
CC
> UV
CC
, FAULT returns to high impedance.
Note 3:
When ITRIP < V
ITRIP
, FAULT returns to high-impedance after RCIN pin becomes greater than 8 V (@ V
CC
= 15 V).
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