NB100LVEP91
2.5 V/3.3 V Any Level
Positive Input to
-2.5 V/-3.3 V LVNECL
Output Translator
Description
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MARKING DIAGRAMS*
20
20
1
The NB100LVEP91 is a triple any level positive input to NECL
output translator. The device accepts LVPECL, LVTTL, LVCMOS,
HSTL, CML or LVDS signals, and translates them to differential
LVNECL output signals (−2.5 V /
−3.3
V).
To accomplish the level translation the LVEP91 requires three
power rails. The V
CC
pins should be connected to the positive power
supply, and the V
EE
pin should be connected to the negative power
supply. The GND pins are connected to the system ground plane. Both
V
EE
and V
CC
should be bypassed to ground via 0.01
mF
capacitors.
Under open input conditions, the D input will be biased at V
CC
/2
and the D input will be pulled to GND. These conditions will force the
Q outputs to a low state, and Q outputs to a high state, which will
ensure stability.
The V
BB
pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to V
BB
as a switching reference voltage.
V
BB
may also rebias AC coupled inputs. When used, decouple V
BB
and V
CC
via a 0.01
mF
capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, V
BB
should be left open.
Features
NB100LVEP91
AWLYYWWG
SO−20 WB
DW SUFFIX
CASE 751D
1
24
1
24
1
24 PIN QFN
MN SUFFIX
CASE 485L
A
WL, L
YY, Y
WW, W
G or
G
N100
VP91
ALYWG
G
•
•
•
•
Maximum Input Clock Frequency > 2.0 GHz Typical
Maximum Input Data Rate > 2.0 Gb/s Typical
500 ps Typical Propagation Delay
Operating Range: V
CC
= 2.375 V to 3.8 V;
V
EE
=
−2.375
V to
−3.8
V; GND = 0 V
•
Q Output will Default LOW with Inputs Open or at GND
•
Pb−Free Packages are Available*
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2008
July, 2008
−
Rev. 18
1
Publication Order Number:
NB100LVEP91/D
NB100LVEP91
Positive Level
Input
D0
R1
D0
R1
D1
R1
D1
R1
D2
R1
D2
R1
NECL Output
Q0
R2
Q0
Q1
R2
Q1
V
CC
V
BB
GND
Q2
R2
Q2
V
EE
Figure 1. Logic Diagram
Table 1. PIN DESCRIPTION
Pin
SOIC
1, 20
QFN
3, 4, 12
Name
V
CC
I/O
−
Default
State
−
Description
Positive Supply Voltage. All V
CC
Pins must be Externally
Connected to Power Supply to Guarantee Proper Opera-
tion.
Negative Supply Voltage. All V
EE
Pins must be Externally
Connected to Power Supply to Guarantee Proper Opera-
tion.
Ground.
ECL Reference Voltage Output
Noninverted Differential Inputs [0:2]. Internal 75 kW to GND.
Inverted Differential Inputs [0:2]. Internal 75 kW to GND and
75 kW to V
CC
. When Inputs are Left Open They Default to
(V
CC
−
GND) / 2.
Noninverted Differential Outputs [0:2]. Typically Terminated
with 50
W
to V
TT
= V
CC
−
2 V
Inverted Differential Outputs [0:2]. Typically Terminated with
50
W
to V
TT
= V
CC
−
2 V
No Connect. The NC Pin is NOT Electrically Connected to
the Die and may Safely be Connected to Any Voltage from
V
EE
to V
CC
.
Exposed Pad. (Note 1)
10
15, 16
V
EE
−
−
14, 17
4, 7
2, 5, 8
3, 6, 9
19, 20, 23,
24
7, 11
5, 8, 13
6, 9, 14
GND
V
BB
D[0:2]
D[0:2]
−
−
LVPECL, LVDS, LVTTL,
LVCMOS, CML, HSTL Input
LVPECL, LVDS,
LVTTL,LVCMOS, CML,
HSTL Input
LVNECL Output
LVNECL Output
−
−
−
Low
High
19,16,13
18,15,12
11
2, 22, 18
1, 21, 17
10
Q[0:2]
Q[0:2]
NC
−
−
−
N/A
−
EP
−
1. The thermally conductive exposed pad on the package bottom (see case drawing) must be attached to a heat sinking conduit and may
only be electrically connected to V
EE
(not GND).
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2
NB100LVEP91
GND GND Q1
24
V
CC
Q0
20
19
Q0 GND Q1 Q1 GND Q2
18
17
16
15
14
13
Q2 NC
12
11
Q0
Q0
V
CC
V
CC
D0
1
V
CC
2
D0
3
4
5
6
7
8
9
D2
10
V
EE
D0 V
BB
D1
D1 V
BB
D2
D0
1
2
3
4
5
6
7
V
BB
8
D1
9
D1
10
11
12
V
CC
NB100LVEP91
23
22
Q1 GND GND
21
20
19
18
17
16
15
14
13
Q2
Q2
V
EE
V
EE
D2
D2
Exposed Pad
(EP)
NB100LVEP91
NC V
BB
Figure 2. SOIC−20 Lead Pinout
(Top View)*
*All V
CC
, V
EE
and GND pins must be externally connected to
a power supply.
Figure 3. QFN−24 Lead Pinout
(Top View)*
*All V
CC
, V
EE
and GND pins must be externally connected to
a power supply. The thermally conductive exposed pad on the
package bottom (see case drawing) must be attached to a
sufficient heat−sinking conduit and may only be electronically
connected to V
EE
(not GND).
Table 2. ATTRIBUTES
Characteristics
Internal Input Pulldown Resistor
Internal Input Pullup Resistor
ESD Protection
(R1)
(R2)
Human Body Model
Machine Model
Charged Device Model
Pb Pkg
SO−20 WB
QFN−24
Flammability Rating
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
2. For additional information, see Application Note AND8003/D.
Oxygen Index: 28 to 34
Level 1
Level 1
Value
75 kW
75 kW
> 2 kV
> 150 V
> 2 kV
Pb−Free Pkg
Level 3
Level 1
Moisture Sensitivity (Note 2)
UL 94 V−0 @ 0.125 in
446 Devices
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3
NB100LVEP91
Table 3. MAXIMUM RATINGS
Symbol
V
CC
V
EE
V
I
V
OP
I
out
I
BB
T
A
T
stg
q
JA
q
JA
q
JC
T
sol
Positive Power Supply
Negative Power Supply
Positive Input Voltage
Operating Voltage
Output Current
PECL V
BB
Sink/Source
Operating Temperature Range
Storage Temperature Range
Thermal Resistance (Junction−to−Ambient)
JESD 51−3 (1S−Single Layer Test Board)
Thermal Resistance (Junction−to−Ambient)
JESD 51−6 (2S2P Multilayer Test Board) with Filled Thermal Vias
Thermal Resistance (Junction−to−Case)
Wave Solder
Pb
Pb−Free
0 lfpm
500 lfpm
0 lfpm
500 lfpm
Standard Board
SOIC−20
SOIC−20
QFN−24
QFN−24
SOIC−20
QFN−24
Parameter
Condition 1
GND = 0 V
GND = 0 V
GND = 0 V
GND = 0 V
Continuous
Surge
V
I
V
CC
V
CC
−
V
EE
Condition 2
Rating
3.8 to 0
−3.8
to 0
3.8 to 0
7.6 to 0
50
100
±
0.5
−40
to +85
−65
to +150
90
60
37
32
30 to 35
11
225
225
Unit
V
V
V
V
mA
mA
mA
°C
°C
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 4. DC CHARACTERISTICS POSITIVE INPUTS
V
CC
= 2.5 V, V
EE
=
−2.375
to
−3.8
V, GND = 0 V (Note 3)
−40°C
Symbol
I
CC
V
IH
V
IL
V
IHCMR
I
IH
I
IL
Characteristic
Positive Power Supply Current
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
Input HIGH Voltage Common Mode Range
(Differential Configuration) (Note 4)
Input HIGH Current (@ V
IH
)
Input LOW Current (@ V
IL
)
D
D
0.5
−150
Min
10
1335
GND
0
Typ
14
Max
20
V
CC
875
2.5
150
0.5
−150
Min
10
1335
GND
0
25°C
Typ
14
Max
20
V
CC
875
2.5
150
0.5
−150
Min
10
1335
GND
0
85°C
Typ
14
Max
20
V
CC
875
2.5
150
Unit
mA
mV
mV
V
mA
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
3. Input parameters vary 1:1 with V
CC
. V
CC
can vary +1.3 V /
−0.125
V.
4. V
IHCMR
min varies 1:1 with GND. V
IHCMR
max varies 1:1 with V
CC
.
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NB100LVEP91
Table 5. DC CHARACTERISTICS POSITIVE INPUT
V
CC
= 3.3 V; V
EE
=
−2.375
V to
−3.8
V; GND = 0 V (Note 5)
−40°C
Symbol
I
CC
V
IH
V
IL
V
BB
V
IHCMR
I
IH
I
IL
Characteristic
Positive Power Supply Current
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
PECL Output Voltage Reference
Input HIGH Voltage Common Mode Range
(Differential Configuration) (Note 6)
Input HIGH Current (@ V
IH
)
Input LOW Current (@ V
IL
)
D
D
0.5
−150
Min
10
2135
GND
1775
0
1875
Typ
16
Max
24
V
CC
1675
1975
3.3
150
0.5
−150
Min
10
2135
GND
1775
0
1875
25°C
Typ
16
Max
24
V
CC
1675
1975
3.3
150
0.5
−150
Min
10
2135
GND
1775
0
1875
85°C
Typ
16
Max
24
V
CC
1675
1975
3.3
150
Unit
mA
mV
mV
mV
V
mA
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Input parameters vary 1:1 with V
CC
. V
CC
can vary +0.5 /
−0.925
V.
6. V
IHCMR
min varies 1:1 with GND. V
IHCMR
max varies 1:1 with V
CC
.
Table 6. DC CHARACTERISTICS NECL OUTPUT
V
CC
= 2.375 V to 3.8 V; V
EE
=
−2.375
V to
−3.8
V; GND = 0 V (Note 7)
−40°C
Symbol
I
EE
V
OH
V
OL
Characteristic
Negative Power Supply Current
Output HIGH Voltage (Note 8)
Output LOW Voltage (Note 8)
Min
40
−1145
−1945
Typ
50
−1020
−1770
Max
60
−895
−1600
Min
38
−1145
−1945
25°C
Typ
50
−1020
−1770
Max
68
−895
−1600
Min
38
−1145
−1945
85°C
Typ
50
−1020
−1770
Max
68
−895
−1600
Unit
mA
mV
mV
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
7. Output parameters vary 1:1 with GND.
8. All loading with 50
W
resistor to GND
−
2.0 V.
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