19-1459; Rev 2; 3/02
KIT
ATION
EVALU
E
BL
AVAILA
±5V, 1Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier
General Description
Features
o
1Gsps Conversion Rate
o
2.2GHz Full-Power Analog Input Bandwidth
o
>7.5 Effective Bits at f
IN
= 500MHz (Nyquist
Frequency)
o
±0.25LSB INL and DNL
o
50Ω Differential Analog Inputs
o
±250mV Input Signal Range
o
On-Chip, +2.5V Precision Bandgap Voltage
Reference
o
Latched, Differential PECL Digital Outputs
o
Low Error Rate: 10
-16
Metastable States at 1Gsps
o
Selectable 8:16 Demultiplexer
o
Internal Demux Reset Input with Reset Output
o
192-Contact ESBGA Package
MAX104
The MAX104 PECL-compatible, 1Gsps, 8-bit analog-to-
digital converter (ADC) allows accurate digitizing of
analog signals with bandwidths to 2.2GHz. Fabricated
on Maxim’s proprietary advanced GST-2 bipolar
process, the MAX104 integrates a high-performance
track/hold (T/H) amplifier and a quantizer on a single
monolithic die.
The innovative design of the internal T/H, which has an
exceptionally wide 2.2GHz full-power input bandwidth,
results in high performance (greater than 7.5 effective
bits) at the Nyquist frequency. A fully differential com-
parator design and decoding circuitry reduce out-of-
sequence code errors (thermometer bubbles or sparkle
codes) and provide excellent metastable performance
of one error per 10
16
clock cycles. Unlike other ADCs
that can have errors resulting in false full- or zero-scale
outputs, the MAX104 limits the error magnitude to
1LSB.
The analog input is designed for either differential or
single-ended use with a ±250mV input voltage range.
Dual, differential, PECL-compatible output data paths
ensure easy interfacing and include an 8:16 demulti-
plexer feature that reduces output data rates to one-half
the sampling clock rate. The PECL outputs can be
operated from any supply between +3V to +5V for com-
patibility with +3.3V or +5V referenced systems. Control
inputs are provided for interleaving additional MAX104
devices to increase the effective system sampling rate.
The MAX104 is packaged in a 25mm x 25mm, 192-con-
tact Enhanced Super-Ball Grid Array (ESBGA™) and is
specified over the commercial (0°C to +70°C) tempera-
ture range.
Ordering Information
PART
MAX104CHC
TEMP RANGE
0°C to +70°C
PIN-PACKAGE
192 ESBGA
192-Contact ESBGA
Ball Assignment Matrix
TOP VIEW
Applications
Digital RF/IF Signal Processing
Direct RF Downconversion
High-Speed Data Acquisition
Digital Oscilloscopes
High-Energy Physics
Radar/Sonar/ECM Systems
ATE Systems
Typical Operating Circuit appears at end of data sheet.
MAX104
ESBGA
ESBGA is a trademark of Amkor/Anam.
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
±5V, 1Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier
MAX104
ABSOLUTE MAXIMUM RATINGS
V
CC
A to GNDA .........................................................-0.3V to +6V
V
CC
D to GNDD.........................................................-0.3V to +6V
V
CC
I to GNDI ............................................................-0.3V to +6V
V
CC
O to GNDD ........................................-0.3V to (V
CC
D + 0.3V)
AUXEN1, AUXEN2 to GND .....................-0.3V to (V
CC
D + 0.3V)
V
EE
to GNDI..............................................................-6V to +0.3V
Between GNDs......................................................-0.3V to +0.3V
V
CC
A to V
CC
D .......................................................-0.3V to +0.3V
V
CC
A to V
CC
I.........................................................-0.3V to +0.3V
PECL Digital Output Current ...............................................50mA
REFIN to GNDR ........................................-0.3V to (V
CC
I + 0.3V)
REFOUT Current ................................................+100µA to -5mA
ICONST, IPTAT to GNDI .......................................-0.3V to +1.0V
TTL/CMOS Control Inputs (DEMUXEN,
DIVSELECT)..........................................-0.3V to (V
CC
D + 0.3V)
RSTIN+, RSTIN- ......................................-0.3V to (V
CC
O + 0.3V)
VOSADJ Adjust Input ................................-0.3V to (V
CC
I + 0.3V)
CLK+ to CLK- Voltage Difference..........................................±3V
CLK+, CLK-.....................................(V
EE
- 0.3V) to (GNDD + 1V)
CLKCOM.........................................(V
EE
- 0.3V) to (GNDD + 1V)
VIN+ to VIN- Voltage Difference ............................................±2V
VIN+, VIN- to GNDI................................................................±2V
Continuous Power Dissipation (T
A
= +70°C)
192-Contact ESBGA (derate 61mW/°C above +70°C) ......4.88W
(with heatsink and 200 LFM airflow,
derate 106mW/°C above +70°C) ........................................8.48W
Operating Temperature Range
MAX104CHC........................................................0°C to +70°C
Operating Junction Temperature.....................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(V
CC
A = V
CC
I = V
CC
D = +5.0V ±5%, V
EE
= -5.0V ±5%, V
CC
O = +3.0V to V
CC
D, REFIN connected to REFOUT, T
A
= T
MIN
to T
MAX
,
unless otherwise noted. Typical values are at T
A
= +25°C.)
PARAMETER
ACCURACY
Resolution
Integral Nonlinearity (Note 1)
Differential Nonlinearity (Note 1)
Missing Codes
ANALOG INPUTS
Full-Scale Input Range
Common-Mode Input Range
Input Resistance
Input Resistance Temperature
Coefficient
VOS ADJUST CONTROL INPUT
Input Resistance (Note 2)
Input V
OS
Adjust Range
REFERENCE INPUT AND OUTPUT
Reference Output Voltage
Reference Output Load
Regulation
Reference Input Resistance
REFOUT
Driving REFIN input only
2.475
2.50
2.525
5
4
5
V
mV
kΩ
R
VOS
VOSADJ = 0 to 2.5V
14
±4
25
±5.5
kΩ
LSB
V
FSR
V
CM
R
IN
TC
R
Note 1
Signal + offset w.r.t. GNDI
VIN+ and VIN- to GNDI, T
A
= +25°C
49
475
500
±0.8
50
150
51
525
mVp-p
V
Ω
ppm/°C
RES
INL
DNL
T
A
= +25°C
T
A
= +25°C
No missing codes guaranteed
8
-0.5
-0.5
±0.25
±0.25
0.5
0.5
None
Bits
LSB
LSB
Codes
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
∆REFOUT
0 < I
SOURCE
< 2.5mA
R
REF
Referenced to GNDR
2
_______________________________________________________________________________________
±5V, 1Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier
DC ELECTRICAL CHARACTERISTICS (continued)
(V
CC
A = V
CC
I = V
CC
D = +5.0V ±5%, V
EE
= -5.0V ±5%, V
CC
O = +3.0V to V
CC
D, REFIN connected to REFOUT, T
A
= T
MIN
to T
MAX
,
unless otherwise noted. Typical values are at T
A
= +25°C.)
PARAMETER
CLOCK INPUTS
(Note 3)
Clock Input Resistance
Input Resistance Temperature
Coefficient
High-Level Input Voltage
Low-Level Input Voltage
High-Level Input Current
Low-Level Input Current
DEMUX RESET INPUT
(Note 4)
Digital Input High Voltage
Digital Input Low Voltage
PECL DIGITAL OUTPUTS
(Note 5)
Digital Output High Voltage
Digital Output Low Voltage
POWER REQUIREMENTS
Positive Analog Supply Current
Positive Input Supply Current
Negative Input Supply Current
Digital Supply Current
Output Supply Current (Note 6)
Power Dissipation (Note 6)
Common-Mode Rejection Ratio
(Note 7)
Positive Power-Supply Rejection
Ratio (Note 8)
Negative Power-Supply
Rejection Ratio (Note 8)
I
CC
A
I
CC
I
I
EE
I
CC
D
I
CC
O
P
DISS
CMRR
PSRR+
PSRR-
VIN+ = VIN- = ±0.1V
(Note 9)
(Note 10)
40
40
40
-290
480
108
-210
205
75
5.25
68
73
68
340
115
780
150
mA
mA
mA
mA
mA
W
dB
dB
dB
V
OH
V
OL
-1.025
-1.810
-0.880
-1.620
V
V
V
IH
V
IL
-1.165
-1.475
V
V
R
CLK
TC
R
CLK+ and CLK- to CLKCOM, T
A
= +25°C
48
50
150
52
Ω
ppm/°C
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MAX104
TTL/CMOS CONTROL INPUTS (DEMUXEN, DIVSELECT)
V
IH
V
IL
I
IH
I
IL
V
IH
= 2.4V
V
IL
= 0
-1
2.0
0.8
50
1
V
V
µA
µA
_______________________________________________________________________________________
3
±5V, 1Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier
MAX104
AC ELECTRICAL CHARACTERISTICS
(V
CC
A = V
CC
I = V
CC
D = 5.0V, V
EE
= -5.0V, V
CC
O = 3.3V, REFIN connected to REFOUT, f
S
= 1Gsps, f
IN
at -1dBFS, T
A
= +25°C,
unless otherwise noted.)
PARAMETER
ANALOG INPUT
Analog Input Full-Power
Bandwidth
Analog Input VSWR
Transfer Curve Offset
DYNAMIC SPECIFICATIONS
ENOB
1000
Effective Number of Bits
(Note 11)
ENOB
500
ENOB
125
SNR
1000
Signal-to-Noise Ratio
(No Harmonics)
SNR
500
SNR
125
THD
1000
Total Harmonic Distortion
(Note 12)
THD
500
THD
125
SFDR
1000
Spurious-Free Dynamic Range
SFDR
500
SFDR
125
SINAD
1000
Signal-to-Noise Ratio and
Distortion
SINAD
500
SINAD
125
Two-Tone Intermodulation
IMD
f
IN
= 1000MHz
f
IN
= 500MHz
f
IN
= 125MHz
f
IN
= 1000MHz
f
IN
= 500MHz
f
IN
= 125MHz
f
IN
= 1000MHz
f
IN
= 500MHz
f
IN
= 125MHz
f
IN
= 1000MHz
f
IN
= 500MHz
f
IN
= 125MHz
f
IN
= 1000MHz
f
IN
= 500MHz
f
IN
= 125MHz
Differential
Single-ended
Differential
Single-ended
Differential
Single-ended
Differential
Single-ended
Differential
Single-ended
Differential
Single-ended
Differential
Single-ended
Differential
Single-ended
Differential
Single-ended
Differential
Single-ended
Differential
Single-ended
Differential
Single-ended
Differential
Single-ended
Differential
Single-ended
Differential
Single-ended
45.3
44.1
62
50
45.4
44.2
7.4
7.2
7.52
7.40
7.55
7.49
7.74
7.73
46.4
46.4
47.0
47.1
47.4
47.4
-52.6
-49.6
-52.5
-51.3
-66.2
-67.4
52.8
52.5
52.3
52.3
68.9
69.5
46.0
46.3
46.2
45.9
47.3
47.3
-57.7
dB
dB
dB
-61
-50
dB
dB
Bits
BW
-3dB
VSWR
V
OS
f
IN
= 500MHz
VOSADJ control input open
-2
2.2
1.1:1
0
+2
GHz
V/V
LSB
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
f
IN1
= 124MHz, f
IN2
= 126MHz,
at -7dB below full-scale
4
_______________________________________________________________________________________
±5V, 1Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier
AC ELECTRICAL CHARACTERISTICS (continued)
(V
CC
A = V
CC
I = V
CC
D = +5.0V, V
EE
= -5.0V, V
CC
O = +3.3V, REFIN connected to REFOUT, f
S
= 1Gsps, f
IN
at -1dBFS, T
A
= +25°C,
unless otherwise noted.)
PARAMETER
TIMING CHARACTERISTICS
Maximum Sample Rate
Clock Pulse Width Low
Clock Pulse Width High
Aperture Delay
Aperture Jitter
Reset Input Data Setup Time
(Note 13)
Reset Input Data Hold Time
(Note 13)
CLK to DREADY Propagation
Delay
DREADY to DATA Propagation
Delay (Note 14)
DATA Rise Time
DATA Fall Time
DREADY Rise Time
DREADY Fall Time
Primary Port Pipeline
Delay
Auxiliary Port Pipeline
Delay
Note 1:
f
MAX
t
PWL
t
PWH
t
AD
t
AJ
t
SU
t
HD
t
PD1
t
PD2
t
RDATA
t
FDATA
t
RDREADY
t
FDREADY
t
PDP
t
PDA
Figure 17
Figure 17
Figure 4
Figure 4
Figure 15
Figure 15
Figure 17
Figure 17
20% to 80%, C
L
= 3pF
20% to 80%, C
L
= 3pF
20% to 80%, C
L
= 3pF
20% to 80%, C
L
= 3pF
Figures 6, 7, 8
Figures 6, 7, 8
DIV1, DIV2 modes
DIV4 mode
DIV1, DIV2 modes
DIV4 mode
-50
0
0
2.2
150
420
360
220
180
7.5
7.5
8.5
9.5
350
1
0.45
0.45
100
<0.5
5
Gsps
ns
ns
ps
ps
ps
ps
ns
ps
ps
ps
ps
ps
Clock
Cycles
Clock
Cycles
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MAX104
Static linearity parameters are computed from a “best-fit” straight line through the code transition points. The full-scale
range (FSR) is defined as 256 x slope of the line.
Note 2:
The offset control input is a self-biased voltage divider from the internal +2.5V reference voltage. The nominal open-circuit
voltage is +1.25V. It may be driven from an external potentiometer connected between REFOUT and GNDI.
Note 3:
The clock input’s termination voltage can be operated between -2.0V and GNDI. Observe the absolute maximum ratings
on the CLK+ and CLK- inputs.
Note 4:
Input logic levels are measured with respect to the V
CC
O power-supply voltage.
Note 5:
All PECL digital outputs are loaded with 50Ω to V
CC
O - 2.0V. Measurements are made with respect to the V
CC
O power-
supply voltage.
Note 6:
The current in the V
CC
O power supply does not include the current in the digital output’s emitter followers, which is a func-
tion of the load resistance and the V
TT
termination voltage.
Note 7:
Common-Mode Rejection Ratio is defined as the ratio of the change in the transfer-curve offset voltage to the change in
the common-mode voltage, expressed in dB.
Note 8:
Power-Supply Rejection Ratio is defined as the ratio of the change in the transfer-curve offset voltage to the change in
power-supply voltage, expressed in dB.
Note 9:
Measured with the positive supplies tied to the same potential; V
CC
A = V
CC
D = V
CC
I. V
CC
varies from +4.75V to +5.25V.
Note 10:
V
EE
varies from -5.25V to -4.75V.
_______________________________________________________________________________________
5
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