82C52
March 1997
CMOS Serial Controller Interface
Description
The Intersil 82C52 is a high performance programmable
Universal Asynchronous Receiver/Transmitter (UART) and
Baud Rate Generator (BRG) on a single chip. Utilizing the
Intersil advanced Scaled SAJI IV CMOS process, the 82C52
will support data rates up to 1M baud asynchronously with a
16X clock (16MHz clock frequency).
The on-chip Baud Rate Generator can be programmed for
any one of 72 different baud rates using a single industry
standard crystal or external frequency source. A unique pre-
scale divide circuit has been designed to provide standard
RS-232-C baud rates when using any one of three industry
standard crystals (1.8432MHz, 2.4576MHz, or 3.072MHz).
A programmable buffered clock output (CO) is available and
can be programmed to provide either a buffered oscillator or
16X baud rate clock for general purpose system usage.
Features
• Single Chip UART/BRG
• DC to 16MHz (1M Baud) Operation
• Crystal or External Clock Input
• On-Chip Baud Rate Generator - 72 Selectable Baud
Rates
• Interrupt Mode with Mask Capability
• Microprocessor Bus Oriented Interface
• 80C86 Compatible
• Single +5V Power Supply
• Low Power Operation . . . . . . . . . . . . . . . 1mA/MHz Typ
• Modem Interface
• Line Break Generation and Detection
• Operating Temperature Range:
- C82C52 . . . . . . . . . . . . . . . . . . . . . . . . . .0
o
C to +70
o
C
- I82C52 . . . . . . . . . . . . . . . . . . . . . . . . . -40
o
C to +85
o
C
- M82C52 . . . . . . . . . . . . . . . . . . . . . . . -55
o
C to +125
o
C
Ordering Information
PACKAGE
PDIP
PLCC
CERDIP
TEMPERATURE
RANGE
0
o
C to +70
o
C
-40
o
C to +85
o
C
0
o
C to +70
o
C
-40
o
C to +85
o
C
0
o
C to +70
o
C
-40
o
C to +85
o
C
-55
o
C to +125
o
C
SMD#
CLCC
SMD#
-55
o
C to +125
o
C
1M BAUD
CP82C52
IP82C52
CS82C52
IS82C52
CD82C52
ID82C52
MD82C52/B
8501501XA
MR82C52/B
85015013A
PKG. NO.
E28.6
E28.6
N28.45
N28.45
F28.6
F28.6
F28.6
F28.6
J28.A
J28.A
Pinouts
82C52 (PDIP, CERDIP)
TOP VIEW
D1
RD 1
WR 2
D0 3
D1 4
D2 5
D3 6
D4 7
D5 8
D6 9
D7 10
A0 11
A1 12
IX 13
OX 14
28 CSO
27 VCC
26 DR
25 SDI
24 INTR
23 RST
22 TBRE
21 CO
20 RTS
19 DTR
18 DSR
17 CTS
16 GND
15 SDO
D6
D7
A0
9
10
11
12
A1
13
IX
82C52 (PLCC, CLCC)
TOP VIEW
CSO
WR
VCC
27
4
D2
D3
D4
D5
5
6
7
8
3
2
1
28
26
25
24
23
22
21
20
19
SDI
INTR
RST
TBRE
DR
D0
RD
CO
RTS
DTR
14
OX
15
SDO
16
GND
17
CTS
18
DSR
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
©
Intersil Corporation 1999
File Number
2950.1
5-1
82C52
Block Diagram
3 - 10
D0-D7
DATA
BUS
BUFFER
UART
CONTROL AND
STATUS
REGISTERS
INTERNAL DATA BUS
22
26
TBRE
DR
RD
WR
A0
A1
CSO
IX
OX
CO
1
2
11
12
28
13
14
21
READ/WRITE
CONTROL
LOGIC
TRANSMITTER
BUFFER
REGISTER
TRANSMITTER
REGISTER
P
S
15
SDO
PROGRAM-
MABLE
BOUD RATE
GENERATOR
RECEIVER
BUFFER
REGISTER
RECEIVER
REGISTER
P
S
25
SDI
RST
INTR
23
24
CONTROL
LOGIC
MODEM
CONTROL AND
STATUS
REGISTERS
18
17
19
20
DSR
CTS
DTR
RTS
Pin Description
SYMBOL
RD
PIN
NO.
1
TYPE
I
ACTIVE
LEVEL
Low
DESCRIPTION
READ: The RD input causes the 82C52 to output data to the data bus (D0-D7). The data
output depends upon the state of the address inputs (A0-A1). CS0 enables the RD input.
WRITE: The WR input causes data from the data bus (D0-D7) to be input to the 82C52.
Addressing and chip select action is the same as for read operations.
DATA BITS 0-7: The Data Bus provides eight, three-state input/output lines for the transfer of
data, control and status information between the 82C52 and the CPU. For character formats
of less than 8 bits, the corresponding D7, D6 and D5 are considered “don't cares” for data
WRITE operations and are 0 for data READ operations. These lines are normally in a high
impedance state except during read operations. D0 is the Least Significant Bit (LSB) and is the
first serial data bit to be received or transmitted.
ADDRESS INPUTS: The address lines select the various internal registers during CPU bus
operations.
CRYSTAL/CLOCK: Crystal connections for the internal Baud Rate Generator. IX can also be
used as an external clock input in which case OX should be left open.
High
SERIAL DATA OUTPUT: Serial data output from the 82C52 transmitter circuitry. A Mark (1) is
a logic one (high) and Space (0) is logic zero (low). SD0 is held in the Mark condition when
CTS is false, when RST is true, when the Transmitter Register is empty, or when in the Loop
Mode.
GROUND: Power supply ground connection.
CLEAR TO SEND: The logical state of the CTS line is reflected in the CTS bit of the Modem
Status Register. Any change of state in CTS causes INTR to be set true when INTEN and
MIEN are true. A false level on CTS will inhibit transmission of data on the SD0 output and will
hold SD0 in the Mark (high) state. If CTS goes false during transmission, the current character
being transmitted will be completed. CTS does not affect Loop Mode operation.
WR
2
I
Low
D0-D7
3-10
I/O
High
A0, A1
11, 12
I
High
IX, OX
13, 14
I/O
SDO
15
O
GND
CTS
16
17
I
Low
Low
5-2
82C52
Pin Description
SYMBOL
DSR
PIN
NO.
18
(Continued)
ACTIVE
LEVEL
Low
TYPE
I
DESCRIPTION
DATA SET READY: The logical state of the DSR line is reflected in the Modem Status Register.
Any change of state of DSR will cause INTR to be set if INTEN and MIEN are true. The state
of this signal does not affect any other circuitry within the 82C52.
DATA TERMINAL READY: The DTR signal can be set (low) by writing a logic 1 to the appro-
priate bit in the Modem Control Register (MCR). This signal is cleared (high) by writing a logic
0 in the DTR bit in the MCR or whenever a reset (RST = high) is applied to the 82C52.
REQUEST TO SEND: The RTS signal can be set (low) by writing a logic 1 to the appropriate
bit in the MCR. This signal is cleared (high) by writing a logic 0 to the RTS bit in the MCR or
whenever a reset (RST = high) is applied to the 82C52.
CLOCK OUT: This output is user programmable to provide either a buffered IX output or a
buffered Baud Rate Generator (16X) clock output. The buffered IX (Crystal or external clock
source) output is provided when the Baud Rate Select Register (BRSR) bit 7 is set to a zero.
Writing a logic one to BRSR bit 7 causes the CO output to provide a buffered version of the
internal Baud Rate Generator clock which operates at sixteen times the programmed baud
rate. On reset D7 (CO select) is reset to 0.
DTR
19
O
Low
RTS
20
O
Low
CO
21
O
TBRE
22
O
High
TRANSMITTER BUFFER REGISTER EMPTY: The TBRE output is set (high) whenever the
Transmitter Buffer Register (TBR) has transferred its data to the Transmit Register. Application
of a reset (RST) to the 82C52 will also set the TBRE output. TBRE is cleared (low) whenever
data is written to the TBR.
RESET: The RST input forces the 82C52 into an “Idle” mode in which all serial data activities
are suspended. The Modem Control Register (MCR) along with its associated outputs are
cleared. The UART Status Register (USR) is cleared except for the TBRE and TC bits, which
are set. The 82C52 remains in an “Idle” state until programmed to resume serial data activities.
The RST input is a Schmitt triggered input.
INTERRUPT REQUEST: The INTR output is enabled by the INTEN bit in the Modem Control
Register (MCR). The MIEN bit selectively enables modem status changes to provide an input
to the INTR logic. Figure 9 in Design Information shows the overall relationship of these inter-
rupt control signals.
SERIAL DATA INPUT: Serial data input to the 82C52 receiver circuits. A Mark (1) is high, and
a Space (0) is low. Data inputs on SDI are disabled when operating in the loop mode or when
RST is true.
DATA READY: A true level indicates that a character has been received, transferred to the
RBR, and is ready for transfer to the CPU. DR is reset on a data READ of the Receiver Buffer
Register (RBR) or when RST is true.
V
CC
: +5V positive power supply pin. A 0.1µF decoupling capacitor from V
CC
(Pin 27) to GND
(Pin 16) is recommended.
CHIP SELECT: The chip select input acts as an enable signal for the RD and WR input
signals.
RST
23
I
High
INTR
24
O
High
SDI
25
I
High
DR
26
O
High
V
CC
27
High
CS0
28
I
Low
5-3
82C52
Reset
During and after power-up, the 82C52 Reset Input (RST)
must be held high for at least two IX clock cycles in order to
initialize and drive the 82C52 circuits to an idle mode until
proper programming can be done. A high on RST causes
the following events to occur
• Resets the internal Baud Rate Generator (BRG) circuit
clock counters and bit counters. The Baud Rate Select
Register (BRSR) is not affected (except for bit 7 which is
reset to 0).
• Clears the UART Status Register (USR) except for
Transmission Complete (TC) and Transmit Buffer Register
Empty (TBRE) which are set. The Modem Control
Register (MCR) is also cleared. All of the discrete lines,
memory elements and miscellaneous logic associated
with these register bits are also cleared or turned off. Note
that the UART Control Register (UCR) is not affected.
Following removal of the reset condition (RST = low), the
82C52 remains in the idle mode until programmed to its
desired system configuration.
Programming The 82C52
The complete functional definition of the 82C52 is
programmed by the systems software. A set of control words
(UCR, BRSR and MCR) must be sent out by the CPU to
initialize the 82C52 to support the desired communication
format. These control words will program the character
length, number of stop bits, even/odd/no parity, baud rate,
etc. Once programmed, the 82C52 is ready to perform its
communication functions.
The control registers can be written to in any order. However,
the MCR should be written to last because it controls the
interrupt enables, modem control outputs and the receiver
enable bit. Once the 82C52 is programmed and operational,
these registers can be updated any time the 82C52 is not
immediately transmitting or receiving data.
Table 1. Shows the control signals required to access 82C52
internal registers.
UART Control Register (UCR)
The UCR is a write only register which configures the UART
transmitter and receiver circuits. Data bits D7 and D6 are not
used but should always be set to a logic zero (0) in order to
insure software compatibility with future product upgrades.
During the Echo Mode, the transmitter always repeats the
received word and parity, even when the UCR is
programmed with different or no parity. See Figure 1.
D7 D6 D5 D4 D3 D2 D1 D0
Stop Bit
Select
0 = 1 Stop Bits
1 = 1.5 Stop Bits (Tx)
and 1 Stop Bit (Rx)
If 5 Data Bits Selected
1 = 2 Stop Bits for 6, 7
or 8 Data Bits Selected
000 = Tx and Rx Even
001 = Tx and Rx Odd
010 = Tx Even, Rx
Odd
011 = Tx Odd, Rx
Even
100 = Tx Even, Rx
Check Disabled
101 = Tx Odd, Rx
Check Disabled
11X = Generation and
Check Disabled
00 = 5 Bits
01 = 6 Bits
10 = 7 Bits
11 = 8 Bits
TABLE 1.
CS0
0
0
0
0
0
0
0
0
A1
0
0
0
0
1
1
1
1
A0
0
0
1
1
0
0
1
1
WR
0
1
0
1
0
1
0
1
RD
1
0
1
0
1
0
1
0
OPERATION
Data Bus
→
Transmitter Buffer
Register (TBR)
Receiver Buffer Register
(RBR)
→
Data Bus
Data Bus
→
UART Control
Register (UCR)
UART Status Register
(USR)
→
Data Bus
Data Bus
→
Modem Control
Register (MCR)
MCR
→
Data Bus
Data Bus
→
Bit Rate Select
Register (BRSR)
Modem Status Register
(MSR)
→
Data Bus
Parity
Control
Word
Length
Select
Reserved Set to 00 for Future
Product Upgrade
Compatibility
FIGURE 1. UCR
5-4
82C52
Baud Rate Select Register (BRSR)
The 82C52 is designed to operate with a single crystal or
external clock driving the IX input pin. The Baud Rate Select
Register is used to select the divide ratio (one of 72) for the
internal Baud Rate Generator circuitry. The internal circuitry
is separated into two separate counters, a Prescaler and a
Divisor Select. The Prescaler can be set to any one of four
division rates,
÷1, ÷3, ÷4,
or
÷5.
The Prescaler design has been optimized to provide
standard baud rates using any one of three popular crystal
frequencies. By using one of these common system clock
frequencies, 1.8432MHz, 2.4576MHz or 3.072MHz and
Prescaler divide ratios of
÷3, ÷4,
or
÷5
respectively, the
Prescaler output will provide a constant 614.4KHz. When
this frequency is further divided by the Divisor Select
counter, any of the standard baud rates from 50 Baud to
38.4Kbaud can be selected (see Table 2). Non-standard
baud rates up to 1Mbaud can be selected by using different
input frequencies (crystal or an external frequency input up
to 16MHz) and/or different Prescaler and Divisor Select
ratios.
Regardless of the baud rate, the baud rate generator
provides a clock which is 16 times the desired baud rate. For
example, in order to operate at a 1Mbaud data rate, a
16MHz crystal, a Prescale rate of
÷1,
and a Divisor Select
rate of “external” would be used. This would provide a
16MHz clock as the output of the Baud Rate Generator to
the Transmitter and Receiver circuits.
The CO select bit in the BRSR selects whether a buffered
version of the external frequency input (IX input) or the Baud
Rate Generator output (16x baud rate clock) will be output
on the CO output (pin 21). The Baud Rate Generator output
will always be a 50% nominal duty cycle except when “exter-
nal” is selected and the Prescaler is set to
÷3
or
÷5.
D7 D6 D5 D4 D3 D2 D1 D0
Prescaler 00 =
÷
1
Select
01 =
÷
3
10 =
÷
4
11 =
÷
5
Divisor
Select
00000 =
÷
2
00001 =
÷
4
00010 =
÷
16/3
00011 =
÷
8
00100 =
÷
32/3
00101 =
÷
16
00110 =
÷
58/3
00111 =
÷
22
01000 =
÷
32
01001 =
÷
64
01010 =
÷
128
01011 =
÷
192
01100 =
÷
256
01101 =
÷
288
01110 =
÷
352
01111 =
÷
512
10000 =
÷
768
11111 = External (÷ 1)
0 = IX Output
1 = Brg Output (On
Reset, D7 (CO Select)
is Reset to 0)
TABLE 2.
BAUD RATE
38.4K
19.2K
9600
7200
4800
3600
2400
2000†
1800†
1200
600
300
200
150
134.5†
110†
75
50
DIVISOR
External
2
4
16/3
8
32/3
16
58/3
22
32
64
128
192
256
288
352
512
768
NOTE: These baud rates are based upon the following input
frequency/ Prescale divisor combinations.
1.8432MHz and Prescale =
÷
3
2.4576MHz and Prescale =
÷
4
3.072MHZ and Prescale =
÷
5
†
All baud rates are exact except for:
BAUD RATE
1800
2000
134.5
110
ACTUAL
1745.45
1986.2
133.33
109.09
PERCENT ERROR
3.03%
0.69%
0.87%
0.83%
Modem Control Register
The MCR is a general purpose control register which can be
written to and read from. The RTS and DTR outputs are
directly controlled by their associated bits in this register.
Note that a logic one asserts a true logic level (low) at these
output pins. The Interrupt Enable (INTEN) bit is the overall
control for the INTR output pin. When INTEN is false, INTR
is held false (low).
The Operating Mode bits configure the 82C52 into one of
four possible modes. “Normal” configures the 82C52 for nor-
mal full or half duplex communications. “Transmit Break”'
enables the transmitter to only transmit break characters
(Start, Data and Stop bits all are logic zero). The Echo Mode
causes any data that is received on the SDI input pin to be
retransmitted on the SDO output pin. Note that this output is
a buffered version of the data seen on the SDI input and is
not a resynchronized output. Also note that normal UART
transmission via the Transmitter Register is disabled when
operating in the Echo mode (see Figure 4). The Loop Test
Mode internally routes transmitted data to the receiver
circuitry for the purpose of self test. The transmit data is
CO
Select
FIGURE 2. BRSR
5-5
FPGA/CPLD
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