82C59A
March 1997
CMOS Priority Interrupt Controller
Description
The Intersil 82C59A is a high performance CMOS Priority
Interrupt Controller manufactured using an advanced 2µm
CMOS process. The 82C59A is designed to relieve the sys-
tem CPU from the task of polling in a multilevel
priority system. The high speed and industry standard
configuration of the 82C59A make it compatible with micro-
processors such as 80C286, 80286, 80C86/88, 8086/88,
8080/85 and NSC800.
The 82C59A can handle up to eight vectored priority inter-
rupting sources and is cascadable to 64 without additional
circuitry. Individual interrupting sources can be masked or
prioritized to allow custom system configuration. Two modes
of operation make the 82C59A compatible with both 8080/85
and 80C86/88/286 formats.
Static CMOS circuit design ensures low operating power.
The Intersil advanced CMOS process results in performance
equal to or greater than existing equivalent products at a
fraction of the power.
Features
• 12.5MHz, 8MHz and 5MHz Versions Available
- 12.5MHz Operation . . . . . . . . . . . . . . . . . . . 82C59A-12
- 8MHz Operation . . . . . . . . . . . . . . . . . . . . . . . 82C59A
- 5MHz Operation . . . . . . . . . . . . . . . . . . . . . . 82C59A-5
• High Speed, “No Wait-State” Operation with 12.5MHz
80C286 and 8MHz 80C86/88
• Pin Compatible with NMOS 8259A
• 80C86/88/286 and 8080/85/86/88/286 Compatible
• Eight-Level Priority Controller, Expandable to
64 Levels
• Programmable Interrupt Modes
• Individual Request Mask Capability
• Fully Static Design
• Fully TTL Compatible
• Low Power Operation
- ICCSB . . . . . . . . . . . . . . . . . . . . . . . . . 10µA Maximum
- ICCOP . . . . . . . . . . . . . . . . . . . . . 1mA/MHz Maximum
• Single 5V Power Supply
• Operating Temperature Ranges
- C82C59A . . . . . . . . . . . . . . . . . . . . . . . . .0
o
C to +70
o
C
- I82C59A . . . . . . . . . . . . . . . . . . . . . . . . -40
o
C to +85
o
C
- M82C59A . . . . . . . . . . . . . . . . . . . . . . -55
o
C to +125
o
C
Ordering Information
PART NUMBER
5MHz
CP82C59A-5
IP82C59A-5
CS82C59A-5
IS82C59A-5
CD82C59A-5
ID82C59A-5
MD82C59A-5/B
5962-8501601YA
MR82C59A-5/B
5962-85016013A
CM82C59A-5
8MHz
CP82C59A
IP82C59A
CS82C59A
IS82C59A
CD82C59A
ID82C59A
MD82C59A/B
5962-8501602YA
MR82C59A/B
5962-85016023A
CM82C59A
12.5MHz
CP82C59A-12
IP82C59A-12
CS82C59A-12
IS82C59A-12
CD82C59A-12
ID82C59A-12
MD82C59A-12/B
-
MR82C59A-12/B
-
CM82C59A-12
SMD#
28 Pad CLCC
SMD#
28 Ld SOIC
0
o
C to +70
o
C
-55
o
C to +125
o
C
CERDIP
28 Ld PLCC
PACKAGE
28 Ld PDIP
TEMPERATURE
RANGE
0
o
C to +70
o
C
-40
o
C to +85
o
C
0
o
C to +70
o
C
-40
o
C to +85
o
C
0
o
C to +70
o
C
-40
o
C to +85
o
C
-55
o
C to +125
o
C
PKG. NO.
E28.6
E28.6
N28.45
N28.45
F28.6
F28.6
F28.6
F28.6
J28.A
J28.A
M28.3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
©
Intersil Corporation 1999
File Number
2784.2
4-1
82C59A
Pinouts
82C59A (PDIP, CERDIP, SOIC)
TOP VIEW
CS 1
WR 2
RD 3
D7 4
D6 5
D5 6
D4 7
D3 8
D2 9
D1 10
D0 11
CAS 0 12
CAS 1 13
GND 14
28 V
CC
27 A0
26 INTA
25 IR7
24 IR6
23 IR5
22 IR4
21 IR3
20 IR2
19 IR1
18 IR0
17 INT
16 SP/EN
15 CAS 2
D6 5
D5 6
D4 7
D3 8
D2 9
D1 10
D0 11
12
CAS 0
13
CAS 1
14
GND
15
CAS 2
16
SP/ EN
17
INT
18
IR0
82C59A (PLCC, CLCC)
TOP VIEW
INTA
26
25 IR7
24 IR6
23 IR5
22 IR4
21 IR3
20 IR2
19 IR1
V
CC
28
INT
WR
RD
CS
D7
A0
27
4
3
2
1
PIN
D7 - D0
RD
WR
A0
CS
CAS 2 - CAS 0
SP/EN
INT
INTA
IR0 - IR7
DESCRIPTION
Data Bus (Bidirectional)
Read Input
Write Input
Command Select Address
Chip Select
Cascade Lines
Slave Program Input Enable
Interrupt Output
Interrupt Acknowledge Input
Interrupt Request Inputs
Functional Diagram
INTA
D
7
-D
0
DATA
BUS
BUFFER
CONTROL LOGIC
RD
WR
A
0
CS
READ/
WRITE
LOGIC
IN -
SERVICE
REG
(ISR)
PRIORITY
RESOLVER
INTERRUPT
REQUEST
REG
(IRR)
IR0
IR1
IR2
IR3
IR4
IR5
IR6
IR7
CAS 0
CAS 1
CAS 2
SP/EN
CASCADE
BUFFER
COMPARATOR
INTERNAL BUS
INTERRUPT MASK REG
(IMR)
FIGURE 1.
4-2
82C59A
Pin Description
SYMBOL
V
CC
GND
CS
WR
RD
D7 - D0
CAS0 - CAS2
SP/EN
PIN
NUMBER
28
14
1
2
3
4 - 11
12, 13, 15
16
TYPE
I
I
I
I
I
I/O
I/O
I/O
DESCRIPTION
V
CC
: The +5V power supply pin. A 0.1µF capacitor between pins 28 and 14 is recommended for
decoupling.
GROUND
CHIP SELECT: A low on this pin enables RD and WR communications between the CPU and the
82C59A. INTA functions are independent of CS.
WRITE: A low on this pin when CS is low enables the 82C59A to accept command words from
the CPU.
READ: A low on this pin when CS is low enables the 82C59A to release status onto the data bus
for the CPU.
BIDIRECTIONAL DATA BUS: Control, status, and interrupt-vector information is transferred via
this bus.
CASCADE LINES: The CAS lines form a private 82C59A bus to control a multiple 82C59A struc-
ture. These pins are outputs for a master 82C59A and inputs for a slave 82C59A.
SLAVE PROGRAM/ENABLE BUFFER: This is a dual function pin. When in the Buffered Mode it
can be used as an output to control buffer transceivers (EN). When not in the Buffered Mode it is
used as an input to designate a master (SP = 1) or slave (SP = 0).
INTERRUPT: This pin goes high whenever a valid interrupt request is asserted. It is used to inter-
rupt the CPU, thus, it is connected to the CPU's interrupt pin.
INTERRUPT REQUESTS: Asynchronous inputs. An interrupt request is executed by raising an
IR input (low to high), and holding it high until it is acknowledged (Edge Triggered Mode), or just
by a high level on an IR input (Level Triggered Mode). Internal pull-up resistors are implemented
on IR0 - 7.
INTERRUPT ACKNOWLEDGE: This pin is used to enable 82C59A interrupt-vector data onto the
data bus by a sequence of interrupt acknowledge pulses issued by the CPU.
ADDRESS LINE: This pin acts in conjunction with the CS, WR, and RD pins. It is used by the
82C59A to decipher various Command Words the CPU writes and status the CPU wishes to read.
It is typically connected to the CPU A0 address line (A1 for 80C86/88/286).
INT
IR0 - IR7
17
18 - 25
O
I
INTA
A0
26
27
I
I
Functional Description
Interrupts in Microcomputer Systems
Microcomputer system design requires that I/O devices such
as keyboards, displays, sensors and other components
receive servicing in an efficient manner so that large
amounts of the total system tasks can be assumed by the
microcomputer with little or no effect on throughput.
The most common method of servicing such devices is the
Polled approach. This is where the processor must test each
device in sequence and in effect “ask” each one if it needs
servicing. It is easy to see that a large portion of the main
program is looping through this continuous polling cycle and
that such a method would have a serious, detrimental effect
on system throughput, thus, limiting the tasks that could be
assumed by the microcomputer and reducing the cost effec-
tiveness of using such devices.
CPU
CPU - DRIVEN
MULTIPLEXER
RAM
I/O (1)
ROM
I/O (2)
I/O (N)
FIGURE 2. POLLED METHOD
4-3
82C59A
A more desirable method would be one that would allow the
microprocessor to be executing its main program and only
stop to service peripheral devices when it is told to do so by
the device itself. In effect, the method would provide an
external asynchronous input that would inform the processor
that it should complete whatever instruction that is currently
being executed and fetch a new routine that will service the
requesting device. Once this servicing is complete, however,
the processor would resume exactly where it left off.
This is the Interrupt-driven method. It is easy to see that sys-
tem throughput would drastically increase, and thus, more
tasks could be assumed by the microcomputer to further
enhance its cost effectiveness.
INT
CPU
The Programmable Interrupt Controller (PlC) functions as an
overall manager in an Interrupt-Driven system. It accepts
requests from the peripheral equipment, determines which
of the incoming requests is of the highest importance (prior-
ity), ascertains whether the incoming request has a higher
priority value than the level currently being serviced, and
issues an interrupt to the CPU based on this determination.
Each peripheral device or structure usually has a special
program or “routine” that is associated with its specific func-
tional or operational requirements; this is referred to as a
“service routine”. The PlC, after issuing an interrupt to the
CPU, must somehow input information into the CPU that can
“point” the Program Counter to the service routine associ-
ated with the requesting device. This “pointer” is an address
in a vectoring table and will often be referred to, in this docu-
ment, as vectoring data.
82C59A Functional Description
PIC
RAM
I/O (1)
ROM
I/O (2)
The 82C59A is a device specifically designed for use in real
time, interrupt driven microcomputer systems. It manages
eight levels of requests and has built-in features for expand-
ability to other 82C59As (up to 64 levels). It is programmed
by system software as an I/O peripheral. A selection of prior-
ity modes is available to the programmer so that the manner
in which the requests are processed by the 82C59A can be
configured to match system requirements. The priority
modes can be changed or reconfigured dynamically at any
time during main program operation. This means that the
complete interrupt structure can be defined as required,
based on the total system environment.
Interrupt Request Register (IRR) and In-Service Register
(ISR)
The interrupts at the IR input lines are handled by two registers
in cascade, the Interrupt Request Register (lRR) and the In-
Service Register (lSR). The IRR is used to indicate all the inter-
rupt levels which are requesting service, and the ISR is used to
store all the interrupt levels which are currently being serviced.
INTA
INT
I/O (N)
FIGURE 3. INTERRUPT METHOD
D
7
- D
0
DATA
BUS
BUFFER
CONTROL LOGIC
RD
WR
A
0
CS
READ/
WRITE
LOGIC
IN
SERVICE
REG
(ISR)
PRIORITY
RESOLVER
INTERRUPT
REQUEST
REG
(IRR)
IR0
IR1
IR2
IR3
IR4
IR5
IR6
IR7
CAS 0
CAS 1
CAS 2
SP/EN
CASCADE
BUFFER
COMPARATOR
INTERNAL BUS
INTERRUPT MASK REG
(IMR)
FIGURE 4. 82C59A FUNCTIONAL DIAGRAM
4-4
82C59A
Priority Resolver
This logic block determines the priorities of the bits set in the
lRR. The highest priority is selected and strobed into the cor-
responding bit of the lSR during the INTA sequence.
Interrupt Mask Register (IMR)
The lMR stores the bits which disable the interrupt lines to
be masked. The IMR operates on the output of the IRR.
Masking of a higher priority input will not affect the interrupt
request lines of lower priority.
Interrupt (INT)
This output goes directly to the CPU interrupt input. The
VOH level on this line is designed to be fully compatible with
the 8080, 8085, 8086/88, 80C86/88, 80286, and 80C286
input levels.
Interrupt Acknowledge (INTA)
INTA pulses will cause the 82C59A to release vectoring
information onto the data bus. The format of this data
depends on the system mode (µPM) of the 82C59A.
Data Bus Buffer
This 3-state, bidirectional 8-bit buffer is used to interface the
82C59A to the System Data Bus. Control words and status
information are transferred through the Data Bus Buffer.
Read/Write Control Logic
The function of this block is to accept output commands from
the CPU. It contains the Initialization Command Word (lCW)
registers and Operation Command Word (OCW) registers
which store the various control formats for device operation.
This function block also allows the status of the 82C59A to
be transferred onto the Data Bus.
Chip Select (CS)
A LOW on this input enables the 82C59A. No reading or
writing of the device will occur unless the device is selected.
Write (WR)
A LOW on this input enables the CPU to write control words
(lCWs and OCWs) to the 82C59A.
Read (RD)
A LOW on this input enables the 82C59A to send the status
of the Interrupt Request Register (lRR), In-Service Register
(lSR), the Interrupt Mask Register (lMR), or the interrupt
level (in the poll mode) onto the Data Bus.
A0
This input signal is used in conjunction with WR and RD sig-
nals to write commands into the various command registers,
as well as to read the various status registers of the chip.
This line can be tied directly to one of the system address
lines.
The Cascade Buffer/Comparator
This function block stores and compares the IDs of all
82C59As used in the system. The associated three I/O pins
(CAS0 - 2) are outputs when the 82C59A is used as a mas-
ter and are inputs when the 82C59A is used as a slave. As a
master, the 82C59A sends the ID of the interrupting slave
device onto the CAS0 - 2 lines. The slave, thus selected will
send its preprogrammed subroutine address onto the Data
Bus during the next one or two consecutive INTA pulses.
(See section “Cascading the 82C59A”.)
Interrupt Sequence
The powerful features of the 82C59A in a microcomputer
system are its programmability and the interrupt routine
addressing capability. The latter allows direct or indirect
jumping to the specified interrupt routine requested without
any polling of the interrupting devices. The normal sequence
of events during an interrupt depends on the type of CPU
being used.
These events occur in an 8080/8085 system:
1. One or more of the INTERRUPT REQUEST lines
(IR0 - IR7) are raised high, setting the corresponding IRR
bit(s).
2. The 82C59A evaluates those requests in the priority
resolver and sends an interrupt (INT) to the CPU, if
appropriate.
3. The CPU acknowledges the lNT and responds with an
INTA pulse.
4. Upon receiving an lNTA from the CPU group, the highest
priority lSR bit is set, and the corresponding lRR bit is
reset. The 82C59A will also release a CALL instruction
code (11001101) onto the 8-bit data bus through D0 - D7.
5. This CALL instruction will initiate two additional INTA
pulses to be sent to 82C59A from the CPU group.
6. These two INTA pulses allow the 82C59A to release its
preprogrammed subroutine address onto the data bus.
The lower 8-bit address is released at the first INTA pulse
and the higher 8-bit address is released at the second
INTA pulse.
7. This completes the 3-byte CALL instruction released by
the 82C59A. In the AEOI mode, the lSR bit is reset at the
end of the third INTA pulse. Otherwise, the lSR bit
remains set until an appropriate EOI command is issued
at the end of the interrupt sequence.
The events occurring in an 80C86/88/286 system are the
same until step 4.
4. The 82C59A does not drive the data bus during the first
INTA pulse.
5. The 80C86/88/286 CPU will initiate a second INTA pulse.
During this INTA pulse, the appropriate ISR bit is set and
the corresponding bit in the IRR is reset. The 82C59A
outputs the 8-bit pointer onto the data bus to be read by
the CPU.
4-5
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