19-1091; Rev 1; 5/04
KIT
ATION
EVALU
BLE
AVAILA
+3.3V, 622Mbps, SDH/SONET
1:4 Deserializer with LVDS Outputs
______________________________Features
♦
Single +3.3V Supply
♦
622Mbps Serial to 155Mbps Parallel Conversion
♦
265mW Power
♦
LVDS Data Outputs and Synchronization Inputs
♦
Synchronization Input for Data Realignment and
Reframing
♦
Differential 3.3V PECL Clock and Data Inputs
_________________General Description
The MAX3681 deserializer is ideal for converting
622Mbps serial data to 4-bit-wide, 155Mbps parallel
data in ATM and SDH/SONET applications. Operating
from a single +3.3V supply, this device accepts PECL
serial clock and data inputs, and delivers low-voltage
differential-signal (LVDS) clock and data outputs for
interfacing with high-speed digital circuitry. It also pro-
vides an LVDS synchronization input that enables data
realignment and reframing.
The MAX3681 is available in the extended-industrial
temperature range (-40°C to +85°C), in a 24-pin SSOP
package.
MAX3681
__________________________Applications
622Mbps SDH/SONET Transmission Systems
622Mbps ATM/SONET Access Nodes
Add/Drop Multiplexers
Digital Cross Connects
________________Ordering Information
PART
MAX3681EAG
MAX3681EAG+
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
24 SSOP
24 SSOP
+Denotes
Lead Free Package
Pin Configuration appears at end of data sheet.
___________________________________________________________________Typical Operating Circuit
V
CC
= +3.3V
V
CC
V
CC
= +3.3V
V
CC
= +3.3V
130Ω
PHOTODIODE
130Ω
SD+
PD3+
100Ω*
MAX3681
PD3-
PD2+
100Ω*
MAX3675
82Ω
LIMITING
AMP
DATA
AND
CLOCK
RECOVERY
130Ω
82Ω
PD2-
PD1+
100Ω*
PD1-
OVERHEAD
TERMINATION
SD-
PREAMP
100Ω
V
CC
= +3.3V
PD0+
100Ω*
130Ω
SCLK+
SCLK-
PCLK-
PD0-
PCLK+
100Ω*
MAX3664
82Ω
82Ω
SYNC+
*REQUIRED ONLY IF OVERHEAD CIRCUIT DOES NOT INCLUDE INTERNAL INPUT TERMINATION.
THIS SYMBOL REPRESENTS A TRANSMISSION LINE OF CHARACTERISTIC IMPEDANCE Z
0
= 50Ω.
GND
SYNC-
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
+3.3V, 622Mbps, SDH/SONET
1:4 Deserializer with LVDS Outputs
MAX3681
ABSOLUTE MAXIMUM RATINGS
Terminal Voltage (with respect to GND)
V
CC
...........................................................................-0.5V to 5V
PECL Inputs (SD+/-, SCLK+/-).................................V
CC
+ 0.5V
LVDS Inputs (SYNC+/-)............................................V
CC
+ 0.5V
Output Current, LVDS Outputs (PCLK+/-, PD_+/-) .............10mA
Continuous Power Dissipation (T
A
= +85°C)
SSOP (derate 8.00mW/°C above +85°C) ......................520mW
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-65°C to +160°C
Lead Temperature (soldering, 10sec) .............................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(V
CC
= +3.0V to +3.6V, differential loads = 100Ω, T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at V
CC
= +3.3V,
T
A
= +25°C.)
PARAMETER
Supply Current
PECL INPUTS
(SD+/-, SCLK+/-)
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Voltage Range
Differential Input Threshold
Threshold Hysteresis
Differential Input Resistance
Output High Voltage
Output Low Voltage
Differential Output Voltage
Change in Magnitude of Differential
Output Voltage for Complementary
States
Output Offset Voltage
Change in Magnitude of Output
Offset Voltage for Complementary
States
Single-Ended Output Resistance
Change in Magnitude of Single-
Ended Output Resistance for
Complementary States
V
IH
V
IL
I
IH
I
IL
V
I
V
IDTH
V
HYST
R
IN
V
OH
V
OL
V
OD
ΔV
OD
V
OS
ΔV
OS
R
O
ΔR
O
40
70
±1
T
A
= +25°C
1.125
0.925
250
400
25
1.275
25
140
±10
85
V
IN
= V
IH(MAX)
V
IN
= V
IL(MAX)
Differential input voltage = 100mV
Common-mode voltage = 50mV
V
CC
- 1.16
V
CC
- 1.81
-10
-10
0
-100
70
100
115
1.475
V
CC
- 0.88
V
CC
- 1.48
10
10
2.4
100
V
V
µA
µA
V
mV
mV
Ω
V
V
mV
mV
V
mV
Ω
%
SYMBOL
I
CC
CONDITIONS
MIN
55
TYP
80
MAX
120
UNITS
mA
LVDS INPUTS AND OUTPUTS
(SYNC+/-, PCLK+/-, PD_+/-)
AC ELECTRICAL CHARACTERISTICS
(V
CC
= +3.0V to +3.6V, differential loads = 100Ω, T
A
= +25°C, unless otherwise noted.) (Note 1)
PARAMETER
Maximum Serial Clock Frequency
Serial Data Setup Time
Serial Data Hold Time
Parallel Clock to Data Output Delay
SYMBOL
f
SCLK
t
SU
t
H
t
CLK-Q
CONDITIONS
MIN
622
800
50
200
550
900
TYP
MAX
UNITS
MHz
ps
ps
ps
Note 1:
AC Characteristics guaranteed by design and characterization.
2
_______________________________________________________________________________________
+3.3V, 622Mbps, SDH/SONET
1:4 Deserializer with LVDS Outputs
MAX3681
__________________________________________Typical Operating Characteristics
(V
CC
= +3.0V to +3.6V, differential loads = 100Ω, unless otherwise noted.)
MAXIMUM SERIAL CLOCK FREQUENCY
vs. TEMPERATURE
MAX3681-01
SERIAL DATA-SETUP TIME
vs. TEMPERATURE
MAX3681-03
SERIAL DATA-HOLD TIME
vs. TEMPERATURE
MAX3681-04
2.0
MAX SERIAL CLOCK FREQUENCY (GHz)
1.8
V
CC
= 3.6V
1.6
1.4
V
CC
= 3.0V
400
SERIAL DATA-SETUP TIME (ps)
360
-100
SERIAL DATA-HOLD TIME (ps)
-140
320
280
-180
-220
1.2
240
-260
1.0
-50
-25
0
25
50
75
100
TEMPERATURE (°C)
200
-50
-25
0
25
50
75
100
TEMPERATURE (°C)
-300
-50
-25
0
25
50
75
100
TEMPERATURE (°C)
SUPPLY CURRENT
vs. TEMPERATURE
MAX3681-02
PARALLEL CLOCK TO DATA
OUTPUT PROPAGATION DELAY
vs. TEMPERATURE
MAX3681-05
120
700
PARALLEL CLOCK TO DATA
PROPAGATION DELAY (ps)
650
SUPPLY CURRENT (mA)
100
V
CC
= +3.6V
V
CC
= +3.3V
600
550
80
V
CC
= +3.0V
60
500
40
-50
-25
0
25
50
75
100
TEMPERATURE (°C)
450
-50
-25
0
25
50
75
100
TEMPERATURE (°C)
_______________________________________________________________________________________
3
+3.3V, 622Mbps, SDH/SONET
1:4 Deserializer with LVDS Outputs
MAX3681
______________________________________________________________Pin Description
PIN
1, 2, 5, 8, 12
3
4
6
7
9, 15, 22
10
11
13
14
16, 18, 20, 23
17, 19, 21, 24
NAME
V
CC
SD+
SD-
SCLK+
SCLK-
GND
SYNC+
SYNC-
PCLK-
PCLK+
PD0- to PD3-
PD0+ to PD3+
+3.3V Supply Voltage
Noninverting PECL Serial Data Input. Data is clocked on the SCLK signal’s positive transition.
Inverting PECL Serial Data Input. Data is clocked on the SCLK signal’s positive transition.
Noninverting PECL Serial Clock Input
Inverting PECL Serial Clock Input
Ground
Noninverting LVDS Synchronizing Pulse Input. Pulse the SYNC signal high for at least two SCLK
periods to shift the data alignment by dropping one bit.
Inverting LVDS Synchronizing Pulse Input. Pulse the SYNC signal high for at least two SCLK
periods to shift the data alignment by dropping one bit.
Inverting LVDS Parallel Clock Output
Noninverting LVDS Parallel Clock Output
Inverting LVDS Parallel Data Outputs. Data is updated on the positive transition of the PCLK signal.
See Figure 2 for the relationship between serial-data-bit position and output-data-bit assignment.
Noninverting LVDS Parallel Data Outputs. Data is updated on the positive transition of the PCLK signal.
See Figure 2 for the relationship between serial-data-bit position and output-data-bit assignment.
FUNCTION
_______________Detailed Description
The MAX3681 deserializer uses a 4-bit shift register,
4-bit parallel output register, 2-bit counter, PECL input
buffers, and low-voltage differential-signal (LVDS)
input/output buffers to convert 622Mbps serial data to
4-bit-wide, 155Mbps parallel data (Figure 1).
The input shift register continuously clocks incoming
data on the positive transition of the serial clock (SCLK)
input signal. The 2-bit counter generates a parallel out-
put clock (PCLK) by dividing down the serial clock fre-
quency. The PCLK signal is used to clock the parallel
output register. During normal operation, the counter
divides the SCLK frequency by four, causing the output
register to latch every four bits of incoming serial data.
The synchronization inputs (SYNC+, SYNC-) are used
for data realignment and reframing. When the SYNC
signal is pulsed high for at least two SCLK cycles, the
parallel output data is delayed by one SCLK cycle. This
realignment is guaranteed to occur within two PCLK
cycles of the SYNC signal’s positive transition. As a
result, the first incoming bit of data during that PCLK
cycle is dropped, shifting the alignment between PCLK
and data by one bit.
See Figure 2 for the functional timing diagram and
Figure 3 for the timing parameters diagram.
SD+
SD-
SCLK+
SCLK-
PECL
PECL
4-BIT
SHIFT
REGISTER
4-BIT
PARALLEL
OUTPUT
REGISTER
LVDS
PD3+
PD3-
PD2+
LVDS
PD2-
PD1+
LVDS
MAX3681
PD1-
PD0+
LVDS
PD0-
PCLK+
SYNC+
SYNC-
100Ω LVDS
2-BIT
COUNTER
LVDS
PCLK-
Figure 1. Functional Diagram
4
_______________________________________________________________________________________
+3.3V, 622Mbps, SDH/SONET
1:4 Deserializer with LVDS Outputs
MAX3681
SCLK
SD
D1-
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
SYNC
PCLK
PD3
D4-
D0
D5
PD2
D3-
D1
D6
PD1
D2-
D2
D7
PD0
D1-
D3
D8
NOTE: SIGNALS SHOWN ARE DIFFERENTIAL. FOR EXAMPLE, SCLK = (SCLK+) - (SCLK-).
Figure 2. Functional Timing Diagram
t
SCLK
= 1 / f
SCLK
SCLK
t
SU
SD
t
H
PCLK
t
CLK-Q
PD0–PD3
NOTE: SIGNALS SHOWN ARE DIFFERENTIAL. FOR EXAMPLE, SCLK = (SCLK+) - (SCLK-).
Figure 3. Timing Parameters
_______________________________________________________________________________________
5
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