MAXIMUM RATINGS
Rating
DC Supply Voltage
DC Supply Current
Operating Ambient Temperature
Storage Temperature Range
Lead Soldering Temperature Range (10 seconds)
Symbol
VDD
IDD
TA
Tstg
—
Limit
+6.0
60
– 40 to + 100
– 65 to +150
+260
Unit
Vdc
mA
°C
°C
°C
ELECTRICAL CHARACTERISTICS
(TA = 25°C, and VCC = 5 V, Tested in Circuit shown in Figure 1 unless otherwise noted)
Characteristic
Supply Voltage
Supply Current
L–Band Gain (Measured from L–Band Input to 47 MHz Output)
IF Gain (Measured from 47 MHz Input to 9.5 MHz Output with Gain
Control at Maximum)
Conversion Gain (Measured from L–Band Input to 9.5 MHz Output with
Gain Control at Maximum)
Gain Control (Externally Adjustable 0 to 5.0 V, Maximum at 0 V)
Noise Figure (Double Sideband)
L–Band Input VSWR (Measured into 50
Ω;
1575.42
±
5.0 MHz)
First IF Output VSWR (Measured into 50
Ω;
47.74
±
5.0 MHz)
Second IF Output VSWR (Measured into 50
Ω;
9.5
±
5.0 MHz)
Input Impedance @ 1st IF 47.7
±
5 MHz (For Reference Only)
Output 1.0 dB Compression Point
First LO (Measured at the First IF Output)
All Other Harmonics (Measured at the First IF Output)
38.1915 MHz Leakage at First IF Output
Second LO (Measured at the Second IF Output)
All Other Harmonics (Measured at Second IF Output)
Reference Oscillator Input
Clock Output
Frequency
Amplitude
Low
HIgh
(Clock Amplitude Measured with the Output Loaded in 15 pF and 40 kΩ)
Duty Cycle
VCO Lock Voltage
Phase Detector Gain
VCO Modulation Sensitivity
Min
4.75
—
—
—
65
—
—
—
—
—
—
—
—
—
—
—
—
400
2Xfref
Typ
—
—
20
45
—
40
9.5
2:1
2:1
2:1
2000
–7
–20
–45
–50
–25
–45
—
—
Max
5.25
60
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
4500
2Xfref
Unit
Vdc
mA
dB
dB
dB
dB
dB
—
—
—
Ω
dBm
dBm
dBm
dBm
dBm
dBm
mVpp
—
2.0
45
1.2
—
—
—
0.16
15
0.8
—
55
3.0
—
—
V
V
%
V
V/Radian
MHz/V
MRFIC1502
2
MOTOROLA RF DEVICE DATA
Table 1. Port Impedance Derived from Circuit Characterization
Zin
Ohms
R
38.3
54.45
43
560
jX
–16.09
11.3
1.5
–850
Pin Number
Pi N
b
44
40
39
32
Pin Name
Pi N
RF IN
TO BPF
FROM BPF
IF OUT
f
(MHz)
1575.42
47.74
47.74
9.5
Zin represents the input impedance of the pin.
APPLICATION INFORMATION
Design Philosophy
The MRFIC1502 design is a standard dual downconver-
sion configuration with an integrated fixed frequency phase–
locked loop to generate the two local oscillators and the
buffer to generate the sampling clock for a digital correlator
and decimator. The active device for the L–band VCO is also
integrated on the chip. This chip is designed in the third
generation of Motorola’s Oxide Self Aligned Integrated
Circuits (MOSAIC 3) silicon bipolar process.
Circuit Considerations
The RF input to the MRFIC1502 is internally matched to 50
ohms. Therefore, only AC coupling is required on the input.
The output of the amplifier is fed directly into the first mixer.
This mixer is an active Gilbert Cell configuration. The output
of the mixer is brought off–chip for filtering of the unwanted
mixer products. The amplifier and mixer have their own VCC
supply (pin 42) in order to reduce the amount of coupling to
the other circuits. There are two bypass capacitors on this
pin, one for the high frequency components and one for the
lower frequency components. These two capacitors should
be placed physically as close to the bias pin as possible to
reduce the inductance in the path. The capacitors should
also be grounded as close to the ground of the IC as
possible, preferably through a ground plane.
The output impedance of the first mixer is 50 ohms, while
the input impedance to the first IF amplifier is 1 kΩ. There is
a trap (zero) designed in at the second LO frequency to limit
the amount of LO leakage into the high gain first IF amplifier.
The first IF amplifier is a variable gain amplifier with 25 dB
of gain and 40 dB of gain control. The gain control pin can be
grounded to provide the maximum gain out of the amplifier. If
the baseband design utilizes a multi–bit A/D converter in the
digital signal processing chip, this amplifier could be used to
control the input to the A/D converter. The amplifier has an
external bypassing capacitor. This capacitor should be on the
order of 0.01
µF,
and again should be located near the
package pin.
The second mixer design is also a Gilbert Cell configura-
tion. The interface between the mixer and the second IF
amplifier is differential in order to increase noise immunity.
This differential interface is also brought off–chip so that
some additional filtering could be added in parallel between
the output of the mixer and input to the amplifier. This filtering
is primarily to reduce the amount of LO leakage into the final
IF amplifier and is achieved using a single 3.9 pF capacitor
across the differential ports. The value of the capacitor
determines the high frequency of the low pass structure.
The supply pin for the IF circuits is pin 33. This supply pin
should be isolated from the other chip supplies in order to
reduce the amount of coupling. The recommended capaci-
tors are a 47 pF and a 0.01
µF,
in parallel to bypass the
supply to ground and should be placed physically as close to
the pin as possible.
The output of the second IF amplifier is 50 ohms with a
bandwidth of
±5.0
MHz. This signal must be filtered before
being digitized in order to limit the noise entering the A/D
converter.
VCO Resonator Design
The design and layout of the circuits around the voltage
controlled oscillator (VCO) are the most sensitive of the
entire layout. The active device and biasing resistors are
integrated on the MRFIC1502. The external circuits consist
of the power supply decoupling, the capacitors for the
integrated supply superfilter, the resonator and frequency
adjusting elements, and the bypassing capacitor on the
emitter of the active device.
The VCO supply is isolated from the rest of the PLL circuits
in order to reduce the amount of noise that could cause
frequency/phase noise in the VCO. The supply should be
filtered using a 22
µH
inductor in series and a 27 pF and
0.01
µF
in parallel. The 27 pF capacitor should be series
resonant at least as high as the VCO frequency to get the
most L–band bypassing as possible. The on–chip supply
filter requires two capacitors off–chip to filter the supply. The
capacitors on the input (pin 8) and output (pin 10) of the filter
are 1.0
µF,
and the output also has a high frequency bypass
capacitor in parallel. The input capacitor should not be smaller
than a 1.0
µF
to insure stability of the supply filter.
The VCO design is a standard negative resistance cell with
a buffer amplifier. The resonating structure is connected to
the base of the active device and consists of a coupling
capacitor, a hyper–abrupt varactor diode, and a wire wound
chip inductor. With the values shown on the application
MRFIC1502
4
MOTOROLA RF DEVICE DATA
circuit, the VCO is centered at 1527.7 MHz, and the gain of
the VCO is approximately 20 MHz/Volt.
The above performance is heavily dependent on the
capacitive structure that is used as the emitter bypass on pin
6. The total capacitance should be approximately 1.0 pF; that
can be achieved using either a discrete element or a
microstrip open circuited stub. The evaluation circuit shown
uses a 0.4 pF capacitor.
Phase–locked Loop Design
The VCO signal at 1527.68 MHz is divided by 40 to get the
second LO frequency of 38.19 MHz. In addition to providing
the LO to the second mixer, the 38 MHz signal is output
through a translator and is used as the sampling clock for the
digital correlator and decimator circuits. There is an addition-
al divide by two so the signal used by the phase detector is at
19.096 MHz. The reference input to the phase detector (pin 18)
has an input sensitivity of 400 mVpp minimum and 2.5 Vpp
maximum.
The loop filter design is the standard op–amp loop filter,
resulting in a type 2 second order loop. The layout of the
discrete components around the loop filter and VCO is very
critical to the performance of the phase–locked loop. Care
should be taken in routing the VCO control voltage line from
the output of the loop filter to the varactor diode.
The output of the divide by 40 is buffered by a clock
translator that converts the low level sine wave into a TTL
level square wave. The loading on the buffer is high so the
peak currents can reach as high as 50 mA with the maximum
load of 1.0 kΩ in parallel with 40 pF on the output. Therefore,
the translator has a dedicated VCC supply, pin 28, which
requires external bypassing and isolation. The recom-
mended bypassing uses two capacitors in parallel, a 47 pF
and a 0.01
µF
capacitor.
Conclusion
The MRFIC1502 offers a highly integrated downconverter
solution for GPS receivers. For more detailed applications
information on GPS system design refer to application note
AN1610, “Using Motorola’s MRFIC1502 in Global Positioning
System Receivers.”
MOTOROLA RF DEVICE DATA
MRFIC1502
5
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