FemtoClock™ Crystal-to-
LVPECL/LVDS/LVCMOS Clock Generator
ICS843S2807
DATA SHEET
G
ENERAL
D
ESCRIPTION
ICS843S2807 is a low phase noise Clock Generator
and is a member of the HiperClockS™ family of high
HiPerClockS™
performance clock solutions from IDT. The device
provides five banks of outputs and a reference clock.
The banks can be enabled by using a common output
enable pin. A 25MHz crystal is used to generate the 50MHz,
66.67MHz, 87.5MHz, 100MHz, 125MHz, 133MHz and 350MHz
frequencies.
F
EATURES
•
Five banks of outputs:
One single-ended LVCMOS reference clock output at: 25MHz
Bank A:
one single-ended (QA0) LVCMOS output at: 133MHz
and one (QA1/nQA1) LVPECL output at: 66.67MHz, 100MHz
and 125MHz
Bank B:
one (QB) LVCMOS output at: 50MHz
Bank C:
one (QC/nQC) differential LVPECL output at: 87.5MHz
Bank D:
one (QD/nQD) differential LVDS output at: 350MHz
•
Crystal input frequency: 25MHz
•
±5% frequency margining
V
CCO
_
LVCMOS
IC
S
P
IN
A
SSIGNMENT
V
CCO
_
LVCMOS
V
CCO
_
LVCMOS
REF_OUT
QA0
V
EE
V
EE
QB
•
Full 3.3V operating supply
•
0°C to 70°C ambient operating temperature
(refer to Table 7 on page 11)
•
Available in lead-free (RoHS 6) package
24
V
CC
QA1
nQA1
V
CCA
1
V
EE
QC
nQC
V
CC
LVCMOS - 133MHz
32 31 30 29 28 27 26 25
F_SEL0
F_SEL1
V
CC
XTAL_IN
XTAL_OUT
V
EE
V
CCA
2
RESET
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
MARGIN
MARGIN_MODE
PLL_BYPASS
nQD
V
CC
OE
V
EE
QD
ICS843S2807
32-Lead LQFP
7mm x 7mm x 1.4mm
package body
Y Package
Top View
23
22
21
20
19
18
17
B
LOCK
D
IAGRAM
LVCMOS - 25MHz
REF_OUT
÷5.2631
F_SEL[1:0]
Pullup
PLL_BYPASS
Pulldown
2
QA0
1
25MHz
LVPECL - 66.67/100/
125MHz
XTAL_IN
OSC
XTAL_OUT
Phase
Detector
VCO
700MHz
0
÷5.6,
÷7,
÷10.5
QA1
nQA1
LVCMOS - 50MHz
÷28
±5%
Frequency
Margining
÷14
QB
LVPECL - 87.5MHz
QC
÷8
nQC
LVDS - 350MHz
QD
MARGIN
Pulldown
MARGIN_MODE
Pulldown
RESET
Pulldown
OE
Pullup
÷2
nQD
ICS843S2807DY REVISION A JULY 20, 2009
1
©2009
Integrated Device Technology, Inc.
ICS843S2807 Data Sheet
FEMTOCLOCK™ CRYSTAL-TO-LVPECL/LVDSLVCMOS CLOCK GENERATOR
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1,
2
3, 16, 17, 24
4,
5
6, 13,
20, 27, 32
7, 21
8
9
10
11
12
14, 15
18, 19
22, 23
25, 29, 30
26
28
31
Name
F_SEL0,
F_SEL1
V
CC
XTAL_IN,
XTAL_OUT
V
EE
V
CCA2,
V
CCA1
RESET
OE
MARGIN
MARGIN_MODE
PLL_BYPASS
QD, nQD
nQC, QC
nQA1, QA1
V
CCO_LVCMOS
QA0
QB
REF_OUT
Type
Input
Power
Input
Power
Power
Input
Input
Input
Input
Input
Output
Output
Output
Power
Output
Output
Output
Pulldown
Pullup
Description
Frequency select pins. See Table 3A. LVCMOS/LVTTL interface levels.
Core supply pins.
Cr ystal oscillator interface. XTAL_OUT is the output. XTAL_IN is the input.
Tuning caps are required for oscillator circuit.
Negative supply pins.
Analog supply pins.
Resets the dividers and PLL. See Table 3C.
LVCMOS/LVTTL interface levels.
Pullup
Output enable pin. See Table 3D. LVCMOS/LVTTL interface levels.
Selects between margin or normal mode. See Table 3B.
Pulldown
LVCMOS/LVTTL interface levels.
Selects between ±5% margin. See Table 3B.
Pulldown
LVCMOS/LVTTL interface levels.
Selects between the PLL and XTAL as the input to the dividers.
Pulldown When LOW, selects PLL. When HIGH, selects XTAL.
LVCMOS/LVTTL interface levels.
Differential Bank D clock outputs. LVDS interface levels.
Differential Bank C clock outputs. LVPECL interface levels.
Differential Bank A clock outputs. LVPECL interface levels.
Output supply pins for LVCMOS/LVTTL outputs.
Single-ended Bank A clock output. 15
Ω
impedance.
LVCMOS/LVTTL interface levels.
Single-ended Bank B clock output. 15
Ω
impedance.
LVCMOS/LVTTL interface levels.
Reference clock output. 15
Ω
impedance. LVCMOS/LVTTL interface levels.
NOTE:
Pullup and Pulldown
refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLDOWN
R
PULLUP
R
OUT
Parameter
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
Output Impedance
QA0, QB, REF_OUT
V
CCO_LVCMOS
= 3.465V
Test Conditions
Minimum
Typical
2
51
51
20
Maximum
Units
pF
kΩ
kΩ
Ω
ICS843S2807DY REVISION A JULY 20, 2009
2
©2009
Integrated Device Technology, Inc.
ICS843S2807 Data Sheet
FEMTOCLOCK™ CRYSTAL-TO-LVPECL/LVDSLVCMOS CLOCK GENERATOR
T
ABLE
3A. F_SEL
X
F
UNCTION
T
ABLE
Inputs
F_SEL1
0
1
1
F_SEL0
1
0
1
QA1 Output Frequency
(MHz)
100
125
66.67 (default)
T
ABLE
3B. MARGIN/MARGIN_MODE F
UNCTION
T
ABLE
Inputs
MARGIN
0
X
1
MARGIN_MODE
1
0
1
Typical
Operation
-5%
Nominal
+5%
T
ABLE
3C. RESET F
UNCTION
T
ABLE
Inputs
RESET
0 (default)
Operation
Normal operation
T
ABLE
3D. O
UTPUT
E
NABLE
F
UNCTION
T
ABLE
Inputs
OE
0
1 (default)
Outputs
Differential
LVCMOS
Differential
LVCMOS
Operation
Low/High
High-Impedance
Enable
Enable
1
The device is reset
NOTE: The device requires a reset pulse during or after
power-up for output synchronization. Minimum reset
pulse width is 1.6ns.
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
(LVCMOS)
Outputs, I
O
(LVDS)
Continuous Current
Surge Current
Outputs, I
O
(LVPECL)
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Junction-to-Case
Storage Temperature, T
STG
50mA
100mA
71.9°C/W (0 mps)
-65°C to 150°C
10mA
15mA
4.6V
-0.5V to V
CC
+ 0.5V
-0.5V to V
CCO_LVCMOS
+ 0.5V
NOTE:
Stresses beyond those listed under Absolute Maximum
Ratings may cause permanent damage to the device. These rat-
ings are stress specifications only. Functional operation of prod-
uct at these conditions or any conditions beyond those listed in
the
DC Characteristics
or
AC Characteristics
is not implied. Ex-
posure to absolute maximum rating conditions for extended pe-
riods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCO_LVCMOS
= 3.3V ± 5%,T
A
= 0°C
TO
70°C
Symbol
V
CC
V
CCA1
+ V
CCA2
V
CCO_LVCMOS
I
EE
I
CCA1
+ I
CCA2
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
3.135
V
CC
– 0.40
3.135
Typical
3.3
3.3
3.3V
Maximum
3.465
V
CC
3.465
265
40
Units
V
V
V
mA
mA
ICS843S2807DY REVISION A JULY 20, 2009
3
©2009
Integrated Device Technology, Inc.
ICS843S2807 Data Sheet
FEMTOCLOCK™ CRYSTAL-TO-LVPECL/LVDSLVCMOS CLOCK GENERATOR
T
ABLE
4B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
CC
= V
CCO_LVCMOS
= 3.3V ± 5%,T
A
= 0°C
TO
70°C
Symbol Parameter
V
IH
V
IL
I
IH
Input High Voltage
Input Low Voltage
Input High Current
PLL_BYPASS, RESET,
MARGIN, MARGIN_MODE
OE, F_SEL[1:0]
PLL_BYPASS, RESET,
MARGIN, MARGIN_MODE
OE, F_SEL[1:0]
QA0, QB, REF_OUT
QA0, QB, REF_OUT
V
CC
= V
IN
= 3.465V
Test Conditions
Minimum Typical
2
-0.3
Maximum
V
CC
+ 0.3
0.8
150
10
V
CC
= 3.465V, V
IN
= 0V
-10
-150
I
OH
= -12mA
I
OL
= 12mA
2.6
0.5
Units
V
V
µA
µA
µA
µA
V
V
I
IL
V
OH
V
OL
Input Low Current
Output High Voltage
Output Low Voltage
T
ABLE
4C. LVDS DC C
HARACTERISTICS
,
V
CC
= 3.3V ± 5%,T
A
= 0°C
TO
70°C
Symbol
V
OD
Δ
V
OD
V
OS
Δ
V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
1.05
1.20
Test Conditions
Minimum
335
Typical
400
Maximum
460
50
1.35
50
Units
mV
mV
V
mV
T
ABLE
4D. LVPECL DC C
HARACTERISTICS
,
V
CC
= 3.3V ± 5%,T
A
= 0°C
TO
70°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
V
CC
- 1.4
V
CC
- 2.0
0.6
Typical
Maximum
V
CC
- 0.9
V
CC
- 1.7
1.2
Units
V
V
V
NOTE 1: Outputs terminated with 50
Ω
to V
CC
- 2V.
T
ABLE
5. C
RYSTAL
C
HARACTERISTICS
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
NOTE: Characterized using an 18pF parallel resonant crystal.
NOTE: Tuning caps are required for oscillator circuit.
Test Conditions
Minimum
Typical
Fundamental
25
50
7
MHz
Ω
pF
Maximum
Units
ICS843S2807DY REVISION A JULY 20, 2009
4
©2009
Integrated Device Technology, Inc.
ICS843S2807 Data Sheet
FEMTOCLOCK™ CRYSTAL-TO-LVPECL/LVDSLVCMOS CLOCK GENERATOR
T
ABLE
6. AC C
HARACTERISTICS
,
V
CC
= V
CCO_LVCMOS
= 3.3V ± 5%,T
A
= 0°C
TO
70°C
Symbol
Parameter
QD/nQD
QA0
QA1/nQA1
f
OUT
Output Frequency
QA1/nQA1
QA1/nQA1
QB
QC/nQC
REF_OUT
REF_OUT
QA0
QB
Cycle-to-Cycle Jitter ;
NOTE 1
66MHz
QA1/nQA1
QC/nQC
QD/nQD
REF_OUT
QA0
QB
Period Jitter, Peak-to-Peak;
NOTE 2
66MHz
QA1/nQA1
QC/nQC
QD/nQD
QA0, QB,
REF_OUT
QA1/nQA1,
QC/nQC
QD/nQD
QA0
QB
odc
Output Duty Cycle
100MHz
125MHz
100MHz
125MHz
F_SEL1 = 1, F_SEL0 = 1
F_SEL1 = 0, F_SEL0 = 1
F_SEL1 = 1, F_SEL0 = 0
Test Conditions
Minimum
Typical
350
133
66.67
100
125
50
87.5
25
150
75
75
50
50
50
50
50
150
110
150
80
150
100
130
100
20% to 80%
20% to 80%
20% to 80%
0.385
90
10 0
45
48
1.25
300
200
100
55
52
Maximum
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ns
ps
ps
ms
%
%
t
jit(cc)
t
jit(per)
t
R
/ t
F
Output Rise/Fall Time
t
L
PLL Lock Time
REF_OUT
40
60
%
QA1/nQA1,
48
52
%
QC/nQC
QD/nQD
48
52
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the
device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after
thermal equilibrium has been reached under these conditons.“
NOTE 1: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 2: Peak-to-Peak measurement based on BER of 1E-7 (N = 10.399).
ICS843S2807DY REVISION A JULY 20, 2009
5
©2009
Integrated Device Technology, Inc.
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