73M2901C/5V
V.22bis Single Chip Modem
DATA SHEET
JULY 2005
DESCRIPTION
The 73M2901C/5V is a single-chip modem that
combines all the controller (DTE) and data pump
functions necessary to implement an intelligent
V.22bis data modem. This device is based on
TERIDIAN Semiconductor’s implementation of the
industry standard 8032 microcontroller core with a
proprietary multiply and accumulate (MAC)
coprocessor; Sigma-Delta A/D and D/A converters;
and an analog front end. The ROM and RAM
necessary to operate the modem are contained on
the device. Additionally, the 73M2901C/5V provides
an on-chip oscillator and Hybrid driver.
The 73M2901C/5V is a high performance, low
voltage, low power, single chip modem capable of
data transmission and reception through 2400bps.
The 73M2901C/5V is intended for embedded
applications and battery operation. This device
offers options for a low power conventional 5-volt
design with optional internal hybrid and country
specific call progress support.
FEATURES
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•
•
•
True one chip solution for embedded
systems
Low operating power (~250mW @ 5V, with
standby and power down mode available)
Designed for +5 volts (+/-10%)
Data speeds:
V.22bis – 2400bps
V.22/Bell 212 – 1200bps
V.21/Bell 103 – 300bps
V.23 – 1200/75bps (with PAVI turnaround)
Bell 202 – 1200bps
Bell 202/V23 4-wire operations
International Call Progress Support (FCC68,
CTR21, JATE…)
Host access to modem port pins via AT
commands for custom I/O expansion
DTMF tone generation and detection
On chip optional hybrid driver
Worldwide Caller ID capability
Blacklisting capability
Line-In-Use and Parallel Pick-Up (911)
detection capability
Manufacturing Self Test capability
Packaging: 32 pin PLCC or 44 pin TQFP
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BLOCK DIAGRAM
Page: 1 of 18
©
2005 TERIDIAN Semiconductor Corporation
Rev 3.0
73M2901C/5V
V.22bis Single Chip Modem
DATA SHEET
HARDWARE DESCRIPTION
The 73M2901C/5V is designed for a single +5 volt
supply with low power consumption (~250mW @ 5
volts). The modem supports automatic standby idle
mode. The modem will also accept a request to
power down from the DTE via hardware control. No
additional major components are required to
complete the modem core logic.
The modem
provides direct firmware LED support via port pins.
HARDWARE FEATURES
•
•
•
•
•
•
Fully self-contained. “AT” Command interpreter
and data pump
User pin available
Synchronous serial data I/O available
Asynchronous serial port
On-chip hybrid driver.
Autobaud capability from 300bps to 9600bps
The hybrid configuration is controlled by the state of
the HBDEN pin. For driving a line-coupling
transformer, HBDEN should be pulled high. For
driving an external hybrid (load on TXAP and TXAN
is 50kΩ or larger), HBDEN should be pulled low.
The 73M2901C/5V provides firmware control for a
hook relay driver (RELAY) as well as interrupt
support for a ring detect opto-coupler (RING).
INTERRUPT PINS
The external interrupt sources,
DTR, ASRCH
and
RING,
come from dedicated input pins of the same name.
DTR
informs the 73M2901C/5V that the host has
requested the 73M2901C/5V perform a specific
function. The actual particulars of that function can
be changed by “AT” commands (described in full in
the TERIDIAN 73M2901C User’s Guide).
RING
informs the 73M2901C/5V that the external
DAA circuitry has detected a ring signal.
CRYSTAL OSCILATOR
The TERIDIAN 73M2901C/5V single chip modem
can use an external 11.0592 MHz reference clock or
can generate such a clock using only a crystal and
two capacitors. If an external clock is used, it should
be applied to OSCIN.
SPECIFYING A CRYSTAL
The manufacturer of a crystal resonator verifies its
frequency of oscillation in a test set-up, but to
ensure that the same frequency is obtained in the
application, the circuit conditions must be the same.
The TERIDIAN 73M2901C/5V modem requires a
parallel mode (antiresonant) crystal, the important
specifications of which are as follows:
Mode:
Frequency:
Frequency tolerance:
Temperature drift:
Load capacitance:
ESR:
Drive level:
Parallel (antiresonant)
11.0592 MHz
±50
ppm
at
initial
temperature.
±50 ppm additional over full
Range.
18pF or 20pF
75Ω max.
Less than 1mW.
POWER SUPPLY
Power is supplied to the 73M2901C/5V via the VPD
and VPA pins. The 73M2901C/5V is designed for a
single +5 (+/-10%) volt supply and for low power
consumption (~250mW @ 5 volts). Ground Reference
is provided at the VND and VNA pins.
LOW POWER MODE
The TERIDIAN 73M2901C/5V supports a low power
mode. If the low power standby option is enabled
the 73M2901C/5V will go into a power saving mode
when idle. The oscillator will be running, clocks will
be supplied to the UART, timers and interrupt
blocks; but no clocks will be supplied to the CPU.
Instruction processing and activity on the internal
busses is halted. Normal operation is resumed when
an interruption such as
DTR, RING
or
ASRCH
(any
character send to the 73M2901C/5V) is requested or
when a reset occurs.
ANALOG LINE / HYBRID INTERFACE
The 73M2901C/5V provides a differential analog
output (TXAP and TXAN) and a single-ended analog
input (RXA) with internal A/D and D/A converters. A
driver is provided for an internal hybrid function.
The internal hybrid driver is capable of driving an
external load matching impedance and a line-
coupling transformer. If an external hybrid is to be
used, the on-chip hybrid drivers can be reconfigured
to drive a minimum load of 50kΩ and thus reduce
the driver’s power consumption.
Page: 2 of 18
©
2005 TERIDIAN Semiconductor Corporation
Rev 3.0
73M2901C/5V
V.22bis Single Chip Modem
DATA SHEET
RESET
A reset is accomplished by holding the RESET pin
high. To ensure a proper power-on reset, the reset
pin must be held high for a minimum of 3µs. At
power on, the voltage at VPD, VPA, and RESET
must come up at the same time for a proper reset.
The signals
DCD, CTS,
and
DSR
will be held
inactive for 25ms, acknowledging the reset operation
within a 250ms time window after the reset
triggerring event. The 73M2901C/5V is ready for
operation after that 250ms window and/or after the
signals
DCD, CTS,
and
DSR
become active.
ASYNCHRONOUS AND SYNCHRONOUS SERIAL
DATA INTERFACE
The serial data interface consists of the TXD and
RXD data paths (LSBit shifted in and out first,
respectively); and the TXCLK and RXCLK serial
clock outputs associated with the data pins;
CTS/RTS
flow control;
DCR, DSR
and
DTR.
In
synchronous mode, the data is passed at the bit rate
(tolerance is +1%, -2.5%).
PIN DESCRIPTIONS
POWER PIN DESCRIPTION
PIN NAME
VPA
VNA
VPD
VND
32-PIN 44-PIN
15
21
6, 25,
29
5, 22,
26
16
22
2,12,
27, 33
11, 24,
44, 28
TYPE
I
I
I
I
DESCRIPTION
Positive analog voltage (+ Analog Supply)
Negative analog voltage. (Analog Ground)
Positive digital voltage (+ Digital Supply)
Negative digital voltage. (Digital Ground)
ANALOG INTERFACE PIN DESCRIPTION
PIN NAME
RXA
TXAN
TXAP
HBDEN
32-PIN 44-PIN
20
16
17
14
21
17
18
15
TYPE
I
O
O
I
DESCRIPTION
Receive analog data
Transmit Analog -
Transmit Analog +
2w/4w hybrid driver enable pin
0 = Driver configured for 50kΩ or greater load (Tie to VND)
1 = Driver configured for driving line-coupling transformer (Tie to
VPD)
VBG
VREF
19
18
20
19
O
O
Analog Band Gap voltage reference pin (0.1µF to VNA)
Analog reference voltage pin (0.1µF to VNA)
EXTERNAL INTERRUPTS PIN DESCRIPTIONS
PIN NAME
RING
DTR
32-PIN 44-PIN
2
32
39
37
TYPE
I
I
DESCRIPTION
External interrupt – Line interface ring detection circuitry input
External interrupt – DTE DTR signal input
Page: 3 of 18
©
2005 TERIDIAN Semiconductor Corporation
Rev 3.0
73M2901C/5V
V.22bis Single Chip Modem
DATA SHEET
PIN DESCRIPTIONS
(continued)
OSCILLATOR PIN DESCRIPTION
PIN NAME
OSCIN
OSCOUT
32-PIN 44-PIN
24
23
26
25
TYPE
I
O
DESCRIPTION
Crystal input for internal oscillator, also input for external
source.
Crystal oscillator output.
DIGITAL INTERFACE PIN DESCRIPTION
PIN NAME
RESET
RXCLK
RXD
TXCLK
TXD
USR10
32-PIN 44-PIN
13
31
30
28
27
12
9
36
35
31
30
8
TYPE
I
O
O
O
I
I/O
DESCRIPTION
Resets 73M2901C/5V
Receive Data Synchronous Clock
Serial output to DTE.
Transmit Data Synchronous Clock
Serial data input from DTE.
This pin can optionally be configured as an active low detect
pin. This can be used to implement such functions as “parallel-
pick-up”, “line-in-use”, or “seize” detect.
Programmable I/O port. This pin can ooptionnaly be used to
control an external switch for Caller ID decoding operations.
Request to Send
Clear to Send
Data Set Ready
Data Carrier Detect
Ring Indicator
Relay driver output
Programmable I/O port
USR11
RTS
(USR12)
CTS
(USR13)
DSR
(USR14)
DCD
(USR15)
RI
(USR16)
RELAY
(USR17)
USR20
11
10
9
8
7
4
3
1
7
6
5
4
3
43
40
38
I/O
I
O
O
O
O
O
I/O
Page: 4 of 18
©
2005 TERIDIAN Semiconductor Corporation
Rev 3.0
73M2901C/5V
V.22bis Single Chip Modem
DATA SHEET
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Operation above maximum rating may permanently damage the device.
PARAMETER
Supply Voltage
Pin Input Voltage
Storage Temperature
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Oscillator Frequency
Operating Temperature
TRANSMITTER
PARAMETER
ITU Guard Tone Power
Calling Tone transmit power
Answer Tone transmit power
Transmit tolerance, all tones
and carriers
CONDITIONS
550Hz (relative to carrier)
1800Hz (relative to carrier)
1300Hz
2225/2100Hz
-1.2
MIN
-5
-8
NOM
-3.5
-6.5
-11.5
-11
1.2
MAX
-2
-5
UNIT
dB
dB
dBm0
1
dBm0
1
dB
RATING
+5.0V (+/-10%)
11.0592MHz +/- 50ppm
-40°C to +85°C
RATING
-0.5V to +7.0V
-0.5V to VPD + 0.5V
-55ºC to 150°C
1
dBm0 refers to the TERIDIAN recommended line interface ( 8dB loss from Transmit pins to the line and 5dB loss from the line to the Receive
2
pin). Results may vary depending on selected DAA. 0dBm = 0.775V
rms
. dBm = 10log {Vrms /[(1mW)(600Ω)]}
©
2005 TERIDIAN Semiconductor Corporation
Page: 5 of 18
Rev 3.0
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