Obsolescence Notice
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PURPOSES ONLY AND IS NOT
RECOMMENDED FOR NEW DESIGNS
ADVANCE INFORMATION
DS3660-1·2
SP8607
600MHz42
4
The SP8607 is an emitter coupled logic divider which
features ECL10K compatible outputs when used with external
pulldown resistors. The inputs are AC coupled.
V
EE
(CASE)
FEATURES
s
ECL Compatible Outputs
s
AC-Coupled Inputs (Internal Bias)
QUICK REFERENCE DATA
OUTPUT
7 8
OUTPUT
6
5 4
V
CC
(0V)
NC
3
1
2
CLOCK INPUT
CLOCK INPUT
s
Supply Voltage:
25·2V
s
Power Consumption: 80mW
s
Temperature Range:
255°C
to
1125°C
(A Grade)
230°C
to
170°C
(B Grade)
INTERNAL BIAS
DECOUPLING
CM8
Fig. 1 Pin connections - bottom view
ABSOLUTE MAXIMUM RATINGS
Supply voltage, V
EE
Output current
Storage temperature range
Max. junction temperature
Max. clock input voltage
28V
10mA
265°C
to
1150°C
1175°C
2·5V p-p
ORDERING INFORMATION
SP8607 A CM
SP8607 B CM
SP8607 AC CM
INTERNAL BIAS
DECOUPLING
3
V
CC
(0V)
5
CLOCK INPUT
CLOCK INPUT
1
2
DIVIDE BY
2
6
7
OUTPUT
OUTPUT
8
V
EE
Fig. 2 Functional diagram
SP8607
ELECTRICAL CHARACTERISTICS
Unless otherwise stated, the Electrical Characteristics are guaranteed over specified supply, frequency and temperature range
Supply voltage, V
CC
= 0V, V
EE
=
25·2V 6
0·25V
Temperature, T
AMB
=
255°C
to
1125°C
(A Grade),
230°C
to
170°C
(B Grade)
Value
Characteristic
Maximum frequency (sinewave input)
Minimum frequency (sinewave input)
Power supply current
Output low voltage
Output high voltage
Minimum output swing
Symbol
f
MAX
f
MIN
I
EE
V
OL
V
OH
V
OUT
Min.
600
40
18
21·4
20·7
Max.
Units
MHz
MHz
mA
V
V
mV
Conditions
Input = 400-800mV p-p
Input = 400-800mV p-p
V
EE
=
25·2V,
outputs unloaded
V
EE
=
25·2V
V
EE
=
25·2V
V
EE
=
25·2V
Notes
21·8
20·85
400
3
3
NOTES
1. The temperature coefficients of V
OH
=
11·63mV/°C,
and V
OL
=
10·34mV/°C
but these are not tested.
2. The test configuration for dynamic testing is shown in Fig.5.
3. Tested at 25°C only.
INPUT AMPLITUDE (mV p-p)
1000
T
AMB
=
255°C
TO
1125°C
800
600
400
200
0
0
100
200
300
INPUT FREQUENCY (MHz)
400
500
600
GUARANTEED
*
OPERATING
WINDOW
*
Tested as specified
in table of Electrical
Characteristics
Fig. 3 Typical input characteristic of SP8607A
j1
j
0.5
j2
j
0.2
j5
0
0.2
0.5
1
2
5
100
200
2
j
0.2
2
j
5
600
500
400
300
2
j
0.5
2
j
1
2
j
2
Fig. 4 Typical input impedance. Test conditions: supply voltage =
25·2V,
ambient
temperature = 25°C, frequencies in MHz, Impedances normalised to 50Ω
2
SP8607
OPERATING NOTES
1. The clock inputs (pins 1 and 2) can be driven single ended or
differentially and should be capacitively coupled to the signal
source. The input signal path is completed by connecting a
capacitor from the internal bias decoupling, pin 3, to ground.
2. In the absence of a signal the device will self-oscillate. If this is
undesirable, it may be prevented by connecting a 15kΩ resistor
from the unused input to V
EE
. This will reduce the input sensitivity
by approximately 100mV.
3. The circuit will operate down to DC but slew rate must be better
than 100V/µs.
4. The outputs are compatible with ECLII. There is an internal load
of 4kΩ on each output. The outputs can be interfaced to ECL10K
by the addition of 1·5kΩ pulldown resistors from the outputs to V
EE
to increase output voltage swing.
5. Input impedance is a function of frequency, See Fig. 4.
6. All components should be suitable for the frequency in use.
1n
GENERATOR
INPUT
33
33
TO SAMPLING
SCOPE
20
2·7k
1
2
1n
3
5
6
450
450
10n
OUTPUT
10n
OUTPUT
3·5k
3·5k
V
EE
1n
DUT
8
7
1n
Fig. 5 Test circuit
1n
INPUT
1
5
6
ECL OUTPUT
440
440
DIVIDE BY
2
7
15k
1n
2
BIAS
4k
4k
1·5k
8
V
EE
1n
1·5k
Fig. 6 Typical application showing interfacing
3
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