Freescale Semiconductor, Inc.
DSP56F827/D
Rev. 9.0, 02/2004
56F827
Technical Data
56F827 16-bit Hybrid Controller
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Up to 40 MIPS at 80MHz core frequency
DSP and MCU functionality in a unified,
C-efficient architecture
Hardware DO and REP loops
64K
×
16-bit words Program Flash
1K
×
16-bit words Program RAM
4K
×
16-bit words Data Flash
4K
×
16-bit words Data RAM
Up to 64K
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16-bit words external memory
expansion each for Program and Data memory
JTAG/OnCE™ for debugging
General Purpose Quad Timer
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MCU-friendly instruction set supports both DSP and
controller functions: MAC, bit manipulation unit, 14
addressing modes
8-channel Programmable Chip Select
10-channel, 12-bit ADC
Synchronous Serial Interface (SSI)
Serial Port Interface (SPI)
Serial Communications Interface (SCI)
Time-of-Day (TOD) Timer
128-pin LQFP Package
16-dedicated and 48 shared GPIO
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EXTBOOT
RESET
DEBUG
IRQB
V
DDIO
V
SSIO
6
JTAG/
OnCE
Port
5
5
V
DD
3
4
V
SS
V
DDA
2
V
SSA
2
IRQA
inputs
10
V
REFP
, V
REFMID
,
V
REFIN
3
V
REFLO
V
REFHI
Program and Boot
Memory
64512 x 16 Flash
1024 x 16 SRAM
ADC
Interrupt
Controller
Low Voltage Supervisor
Analog Reg
Program Controller
and Hardware
Looping Unit
PAB
PDB
Address
Generation
Unit
Data ALU
Bit
16 x 16 + 36
→
36-Bit MAC Manipulation
Three 16-bit Input Registers
Unit
Two 36-bit Accumulators
4
VPP
Quad Timer A/
or GPIO
16-Bit
56800
Core
PLL
CLKO
2
SCI 2 or
GPIO
SSI 0 or
GPI0
SCI 0 &1 or
SPI 0
SPI 1 or
GPIO
Programmable
Chip Select
Dedicated
GPIO
Data Memory
4096 x 16 Flash
4096 x 16 SRAM
6
XDB2
CGDB
XAB1
XAB2
INTERRUPT
CONTROLS
16
COP
RESET
MODULE
CONTROLS
ADDRESS
BUS [8:0]
DATA
BUS [15:0]
Clock
Gen
IPBB
CONTROLS
16
XTAL
EXTAL
4
COP/
Watchdog
4
PCS [2:7}
6
Application-
Specific
Memory &
Peripherals
TOD
Timer
IPBus Bridge
(IPBB)
External
Bus
Interface
Unit
External
Address Bus
Switch
16
A[00:15]
or
GPIOA16[00:16]
External
Data Bus
Switch
16
D[00:15]
or
GPIOG16[00:16]
PS or PCS[0]
DS or PCS[1]
WR
RD
16
Bus
Control
Figure 1. 56F827 Block Diagram
© Motorola, Inc., 2004. All rights reserved.
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Part 1 Overview
1.1 56F827 Features
1.1.1
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Digital Signal Processing Core
Efficient 16-bit 56800 family DSP engine with dual Harvard architecture
As many as 40 Million Instructions Per Second (MIPS) at 80MHz core frequency
Single-cycle 16
×
16-bit parallel Multiplier-Accumulator (MAC)
Two 36-bit accumulators including extension bits
16-bit bidirectional shifter
Parallel instruction set with unique DSP addressing modes
Hardware DO and REP loops
Three internal address buses and one external address bus
Four internal data buses and one external data bus
Instruction set supports both DSP and controller functions
Controller style addressing modes and instructions for compact code
Efficient C Compiler and local variable support
Software subroutine and interrupt stack with depth limited only by memory
JTAG/OnCE Debug Programming Interface
Freescale Semiconductor, Inc...
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1.1.2
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Memory
Harvard architecture permits as many as three simultaneous accesses to Program and Data memory
On-chip memory including a low-cost, high-volume Flash solution
— 64K words of Program Flash
— 1K words of Program RAM
— 4K words of Data RAM
— 4K words of Data Flash
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Off-chip memory expansion capabilities programmable for 0, 4, 8, or 12 wait states
— As much as 64 K
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16 Data memory
— As much as 64 K
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16 Program memory
1.1.3
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Peripheral Circuits for 56F827
One 10 channel, 12-bit, Analog-to-Digital Converter (ADC)
One General Purpose Quad Timer totaling 4 pins
One Serial Peripheral Interface with configurable four-pin port multiplexed with two Serial
Communications Interfaces totalling 4 pins or 4 GPIO pins
Three Serial Communication Interfaces with 2 pins each (or 6 additional GPIO pins)
Two Serial Peripheral Interface with configurable four-pin port (or 4 additional GPIO pins)
2
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56F827 Technical Data
Freescale Semiconductor, Inc.
56F827 Description
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One Synchronous Serial Interface with 6 pins (or 6 additional GPIO pins)
One 8-channel Programmable Chip Select
Sixteen dedicated and forty eight multiplexed GPIO pins (64 total)
Computer-Operating Properly (COP) Watchdog timer
Two external interrupt pins
External reset pin for hardware reset
JTAG/On-Chip Emulation (OnCE™) for unobtrusive, processor speed-independent debugging
Software-programmable, Phase Locked Loop-based frequency synthesizer for the core clock
Fabricated in high-density CMOS with 5V-tolerant, TTL-compatible digital inputs
One Time of Day (TOD) Timer
Freescale Semiconductor, Inc...
1.1.4
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Power Information
Dual power supply, 3.3V and 2.5V
Wait and Multiple Stop modes available
1.2 56F827 Description
The 56F827 is a member of the 56800 core-based family of hybrid controllers. It combines, on a single
chip, the processing power of a DSP and the functionality of a microcontroller with a flexible set of
peripherals to create an extremely cost-effective solution for general purpose applications. Because of its
low cost, configuration flexibility, and compact program code, the 56F827 is well-suited for many
applications. The 56F827 includes many peripherals that are especially useful for applications such as:
noise suppression, ID tag readers, sonic/subsonic detectors, security access devices, remote metering,
sonic alarms, and telephony.
The 56800 core is based on a Harvard-style architecture consisting of three execution units operating in
parallel, allowing as many as six operations per instruction cycle. The microprocessor-style programming
model and optimized instruction set allow straightforward generation of efficient, compact code for both
DSP and MCU applications. The instruction set is also highly efficient for C/C++ Compilers to enable rapid
development of optimized control applications.
The 56F827 supports program execution from either internal or external memories. Two data operands can
be accessed from the on-chip Data RAM per instruction cycle. The 56F827 also provides two external
dedicated interrupt lines, and up to 64 General Purpose Input/Output (GPIO) lines, depending on peripheral
configuration.
The 56F827 controller includes 64K words (16-bit) of Program Flash and 4K words of Data Flash (each
programmable through the JTAG port) with 1K words of Program RAM and 4K words of Data RAM. It
also supports program execution from external memory. The 56800 core is capable of accessing two data
operands from the on-chip Data RAM per instruction cycle.
This controller also provides a full set of standard programmable peripherals that include one 10-input, 12-
bit Analog-to-Digital Converters (ADC), one Synchronous Serial Interface (SSI), two Serial Peripheral
Interfaces (SPI), three Serial Communications Interfaces (SCI). (Note: The second SPI is multiplexed with
the second and third SCIs, giving the option to select a second SPI or two additional SCIs.) This hybrid
controller also provides one Programmable Chip Select (PCS), and one Quad Timer. The SCI, SSI, SPI,
Quad Timer A, and select address and data lines can be used as General Purpose Input/Outputs (GPIOs) if
those functions are not required.
56F827 Technical Data
3
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1.3 Award-Winning Development Environment
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Processor Expert
TM
(PE) provides a Rapid Application Design (RAD) tool that combines easy-to-
use component-based software application creation with an expert knowledge system.
The Code Warrior Integrated Development Environment is a sophisticated tool for code navigation,
compiling, and debugging. A complete set of evaluation modules (EVMs) and development system
cards will support concurrent engineering. Together, PE, Code Warrior and EVMs create a
complete, scalable tools solution for easy, fast, and efficient development.
1.4 Product Documentation
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The four documents listed in
Table 2
are required for a complete description and proper design with the
56F827. Documentation is available from local Motorola distributors, Motorola semiconductor sales
offices, Motorola Literature Distribution Centers, or online at
www.motorola.com/semiconductors.
Table 1. 56F827 Chip Documentation
Topic
DSP56800
Family Manual
DSP56F826/F827
User’s Manual
56F827
Technical Data Sheet
56F827
Product Brief
56F827
Errata
Description
Detailed description of the 56800 family architecture,
and 16-bit core processor and the instruction set
Detailed description of memory, peripherals, and
interfaces of the 56F826 and 56F827
Electrical and timing specifications, pin descriptions,
and package descriptions (this document)
Summary description and block diagram of the 56F827
core, memory, peripherals and interfaces
Details any chip issues that might be present
Order Number
DSP56800FM/D
DSP56F826-827UM/D
DSP56F827/D
DSP56F827PB/D
DSP56F827E/D
1.5 Data Sheet Conventions
This data sheet uses the following conventions:
OVERBAR
“asserted”
“deasserted”
Examples:
This is used to indicate a signal that is active when pulled low. For example, the RESET pin is
active when low.
A high true (active high) signal is high or a low true (active low) signal is low.
A high true (active high) signal is low or a low true (active low) signal is high.
Signal/Symbol
PIN
PIN
PIN
PIN
1.
Logic State
True
False
True
False
Signal State
Asserted
Deasserted
Asserted
Deasserted
Voltage
1
V
IL
/V
OL
V
IH
/V
OH
V
IH
/V
OH
V
IL
/V
OL
Values for VIL, VOL, VIH, and VOH are defined by individual product specifications.
4
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56F827 Technical Data
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Introduction
Part 2 Signal/Connection Descriptions
2.1 Introduction
The input and output signals of the 56F827 are organized into functional groups, as shown in
Table 2
and
as illustrated in
Figure 2. Table 3
describes the signal or signals present on a pin.
Table 2. Functional Group Pin Allocations
Functional Group
Power (V
DD
, V
DDIO,
V
DDA or
V
DDA_ADC
)
Ground (V
SS
, V
SSIO,
V
SSA, or
V
SSA_ADC
)
V
PP
PLL and Clock
Address Bus
1
Data Bus
1
Bus Control
Quad Timer Module Ports
1
JTAG/On-Chip Emulation (OnCE)
Dedicated General Purpose Input/Output
Synchronous Serial Interface (SSI) Port
1
Serial Peripheral Interface (SPI) Port
1
Serial Communications Interface1 (SCI0, SCI1) Port
2
Serial Communications Interface2 (SCI2) Port
1
Analog to Digital Converter (ADC)
Programmable Chip Select (PCS)
3
Interrupt and Program Control
1.
2.
3.
Number of Pins
(3,5,1,1)
(3,5,1,1)
1
3
16
16
4
4
6
16
6
4
4
2
15
6
5
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Alternately, GPIO pins
Alternately, SPI pins
In addition, 2 Bus Control pins can be programmed as PCS[0-1].
56F827 Technical Data
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