6N138,6N139
TOSHIBA Photocoupler
GaAℓAs Ired & Photo IC
6N138, 6N139
Current Loop Driver
Low Input Current Line Receiver
CMOS Logic Interface
The TOSHIBA 6N138 and 6N139 consists of a GaAℓAs infrared emitting
diode coupled with a split-Darlington output configuration.
A high speed GaAℓAs Ired manufactured with an unique LPE junction, has
the virtue of fast rise and fall time at low drive current.
•
Isolation voltage: 2500 Vrms (min)
•
Current transfer ratio
: 6N138
−
300% (min) (I
F
=1.6mA)
: 6N139
−
400% (min) (I
F
=0.5mA)
•
Switching time: 6N138
−
t
PHL
= 10μs (max)
−
t
PLH
= 35μs (max)
6N139
−
t
PHL
= 1μs (max)
−
t
PLH
= 7μs (max)
•
UL recognized: UL1577, file no. E67349
Unit: mm
Pin Configuration (top view)
1 : N .C .
1
8
2 : Anode
3 : C a th o d e
2
7
4 : N .C .
5 : G nd
3
6
6 : O u tp u t
7 : O u tp u t B a s e
8 : V
CC
4
5
TOSHIBA
11−10C4
Weight: 0.54 g (typ.)
Schematic
V
CC
8
2
+
I
F
I
C C
I
O
6
V
O
V
F
-
3
I
B
V
B
7
5
GND
Start of commercial production
1
1988/02
2014-09-01
6N138,6N139
Absolute Maximum Ratings
(
*
) (Ta = 0°C to + 70°C)
Characteristic
Forward current
Pulse forward current
LED
Total pulse forward current
Reverse voltage
Diode power dissipation
Output current
Detector
Emitter−base reverse voltage
Supply voltage
Output voltage
Output power dissipation
Operating temperature range
Storage temperature range
Lead solder temperature (10s)
(*4)
Symbol
(Note 1)
I
F
I
FP
I
FP
(*1)
(*2)
Rating
20
40
1
5
35
60
0.5
−0.5
to 18
−0.5
to 18
100
0 to 70
−55
to 125
260
2500
3540
Unit
mA
mA
A
V
mW
mA
V
V
V
mW
°C
°C
°C
V
rms
V
dc
V
R
(Note 2)
(Note 3)
P
D
I
O
V
EB
V
CC
V
O
(Note 4)
(*3)
(*3)
P
O
T
opr
T
stg
T
sol
BV
S
(**)
Isolation voltage (1minute, R.H.≤ 60%)
Note: Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the
significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if
the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum
ratings.
Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook
(“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test
report and estimated failure rate, etc.).
(*) JEDEC registered data
(**) Not registered JEDEC
(*1) 50% duty cycle, 1ms pulse width
(*2) Pulse width 1μs, 300pps
(*3) 6N138…
−0.5
to 7V
(*4) 1.6mm below seating plane
2
2014-09-01
6N138,6N139
Electrical Characteristics
Over Recommended Temperature
(Ta = 0°C to 70°C, unless otherwise noted)
Characteristic
Symbol
Test Condition
I
F
=0.5mA, V
O
=0.4V
V
CC
=4.5V
CTR(*)
I
F
=1.6mA, V
O
=0.4V
V
CC
=4.5V
I
F
=1.6mA, I
O
=6.4mA
V
CC
=4.5V
Logic low output
voltage
6N139
(Note 6)
V
OL
I
F
=5mA, I
O
=15mA
V
CC
=4.5V
I
F
=12mA, I
O
=24mA
V
CC
=4.5V
I
F
=1.6mA, I
O
=4.8mA
V
CC
=4.5V
I
OH
(*)
I
CCL
I
CCH
V
F
(*)
BV
R
(*)
I
F
=0mA, V
O
=V
CC
=18V
I
F
=0mA, V
O
=V
CC
=7V
I
F
=1.6mA, V
O
=Open
V
CC
=5V
I
F
=0mA, V
O
=Open, V
CC
=5V
I
F
=1.6mA, Ta=25°C
I
R
=10μA, Ta=25°C
Min
400
500
300
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
5
⎯
⎯
(Note 7),
(Note 7)
⎯
⎯
(*5)Typ.
800
900
600
0.1
0.1
0.2
0.1
0.05
0.05
0.2
10
1.65
⎯
−1.9
60
10
12
Max
⎯
⎯
⎯
0.4
0.4
Unit
Current transfer
ratio
6N139
(Note 5, 6)
6N138
%
V
0.4
0.4
100
250
⎯
⎯
1.7
⎯
⎯
⎯
⎯
⎯
μA
mA
nA
V
V
mV / °C
pF
Ω
pF
6N138
Logic high output
current
6N139
(Note 6)
6N138
(Note 6)
Logic high supply current
(Note 6)
Input forward voltage
Input reverse breakdown voltage
Temperature coefficient of forward voltage
Input capacitance
Resistance (input−output)
Capacitance (input−output)
Logic low supply current
∆V
F
/
∆Ta
I
F
=1.6mA
C
IN
R
I−O
C
I−O
f=1MHz, V
F
=0
V
I−O
=500V
R.H.≤ 60%
f=1MHz
0.6
(**) JEDEC registered data.
(*5) All typical values are at Ta=25°C and V
CC
=5V, unless otherwise noted.
3
2014-09-01
6N138,6N139
Switching Specifications
(Ta=25°C, V
CC
=5V, unless otherwise specified)
Characteristic
Propagation delay
time to logic low
at output
(Note 6, 8)
6N139
6N138
6N139
6N138
CM
H
2
Symbol
Test
Circuit
Test Condition
I
F
=0.5mA, R
L
=4.7kΩ
t
pHL
(*)
1
I
F
=12mA, R
L
=270Ω
I
F
=1.6mA, R
L
=2.2kΩ
I
F
=0.5mA, R
L
=4.7kΩ
t
pLH
(*)
1
I
F
=12mA, R
L
=270Ω
I
F
=1.6mA, R
L
=2.2kΩ
I
F
=0mA, R
L
=2.2kΩ
V
CM
=400V
p−p
I
F
=1.6mA
R
L
=2.2kΩ
V
CM
=400V
p−p
Min
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Typ.
5
0.2
1
5
1
4
500
Max
25
1
10
60
7
35
⎯
V /
μs
μs
μs
Unit
Propagation delay
time to logic high
at output
(Note 6, 8)
Common mode transient
immunity at logic high
level output
Common mode transient
immunity at logic low
level output
(Note 9)
(Note 9)
CM
L
2
⎯
−500
⎯
V /
μs
(*)JEDEC registered data.
(Note 1):
(Note 2):
(Note 3):
(Note 4):
(Note 5):
(Note 6):
(Note 7):
(Note 8):
(Note 9):
Derate linearly above 50°C free−air temperature at a rate of 0.4mA / °C
Derate linearly above 50°C free−air temperature at a rate of 0.7mW / °C
Derate linearly above 25°C free−air temperature at a rate of 0.7mA / °C
Derate linearly above 25°C free−air temperature at a rate of 2.0mW / °C
DC CURRENT TRANSFER RATIO is defined as the ratio of output collector current, I
O
, to the forward
LED input current, I
F
, times 100%.
Pin 7 open.
Device considered a two−terminal device: Pins 1, 2, 3, and 4 shorted together and Pins 5, 6, 7 and 8
shorted together.
Use of a resistor between pin 5 and 7 will decrease gain and delay time.
Common mode transient immunity in logic high level is the maximum tolerable (positive) dV
CM
/ dt on
the leading edge of the common mode pulse, V
CM
, to assure that the output will remain in a logic high
state (i.e. V
O
> 2.0V).
Common mode transient immunity in Logic Low level is the maximum tolerable (negative) dV
CM
/ dt on
the trailing edge of the common mode pulse signal, V
CM
, to assure that the output will remain in a logic
low state (i.e. V
O
< 0.8V).
4
2014-09-01
6N138,6N139
Test Circuit 1.
I
F
0
V
O
(Saturated
Response)
1.5V
t
pHL
V
O
(Non-
Saturated
Response)
10%
90%
t
r
90%
10%
t
f
1.5V
t
pLH
5V
5V
Pulse gen.
Zo = 50Ω
t
f
= 5ns
10% Duty cycle
1 / f < 100μs
100Ω
I
F
Monitor
F
I
F
1
2
3
4
8
7
6
5
R
L
+5V
V
OL
V
O
C
L
(*)
(*)C
L
is approximately 15pF which includes probe
and stray wiring capacitance.
Test Circuit 2.
t
r,
t
f
= 0.64μs
90%
t
r
V
O
Switch at A: I
F
= 0mA
V
OL
V
O
Switch at B: I
F
= 1.6mA
Pulse gen
t
f
0V
B
5V
V
FF
A
I
F
1
2
3
4
8
7
6
5
R
CC
R
L
V
O
+5V
400V
V
CM
10%
+
V
CM
－
5
2014-09-01
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