3.3 VOLT CMOS SyncBiFIFO
TM
WITH BUS-MATCHING
16,384 x 36 x 2
IDT72V3684
32,768 x 36 x 2
IDT72V3694
65,536 x 36 x 2
IDT72V36104
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
Memory storage capacity:
IDT72V3684 – 16,384 x 36 x 2
IDT72V3694 – 32,768 x 36 x 2
IDT72V36104 – 65,536 x 36 x 2
Clock frequencies up to 100 MHz (6.5ns access time)
Two independent clocked FIFOs buffering data in opposite
directions
Select IDT Standard timing (using
EFA, EFB, FFA,
and
FFB
flags
functions) or First Word Fall Through Timing (using ORA, ORB,
IRA, and IRB flag functions)
Programmable Almost-Empty and Almost-Full flags; each has five
default offsets (8, 16, 64, 256 and 1,024 )
Serial or parallel programming of partial flags
Retransmit Capability
•
•
•
•
•
Port B bus sizing of 36 bits (long word), 18 bits (word) and 9 bits
(byte)
Big- or Little-Endian format for word and byte bus sizes
Master Reset clears data and configures FIFO, Partial Reset
clears data but retains configuration settings
Mailbox bypass registers for each FIFO
Free-running CLKA and CLKB may be asynchronous or coincident
(simultaneous reading and writing of data on a single clock edge
is permitted)
Auto power down minimizes power dissipation
Available in space saving 128-pin Thin Quad Flatpack (TQFP)
Pin compatible to the lower density parts, IDT72V3624/72V3634/
72V3644/72V3654/72V3664/72V3674
Industrial temperature range (–40°C to +85°C) is available
°
°
Green parts available, see ordering information
FUNCTIONAL BLOCK DIAGRAM
MBF1
Mail 1
Register
Output Bus-
Matching
Input
Register
Output
Register
CLKA
CSA
W/RA
ENA
MBA
MRS1
PRS1
Port-A
Control
Logic
36
RAM ARRAY
16,384 x 36
32,768 x 36
65,536 x 36
36
36
FIFO1,
Mail1
Reset
Logic
36
Write
Pointer
Read
Pointer
Status Flag
Logic
EFB/ORB
AEB
FFA/IRA
AFA
FS2
FS0/SD
FS1/SEN
A
0
-A
35
EFA/ORA
AEA
FIFO1
Programmable Flag
Offset Registers
16
FIFO2
Timing
Mode
FWFT
B
0
-B
35
Status Flag
Logic
Read
Pointer
Write
Pointer
36
FFB/IRB
AFB
36
RT1
RTM
RT2
Output
Register
Input Bus-
Matching
36
16,384 x 36
32,768 x 36
65,536 x 36
Mail 2
Register
36
Input
Register
FIFO1 and
FIFO2
Retransmit
Logic
RAM ARRAY
FIFO2,
Mail2
Reset
Logic
MRS2
PRS2
Port-B
Control
Logic
4677 drw01
MBF2
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SyncBiFIFO is a trademark of Integrated Device Technology, Inc.
CLKB
CSB
W/RB
ENB
MBB
BE
BM
SIZE
COMMERCIAL TEMPERATURE RANGE
©
2009
FEBRUARY 2009
1
DSC-4677/8
Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
IDT72V3684/72V3694/72V36104 3.3V CMOS SyncBiFIFO
TM
WITH
,
BUS-MATCHING 16,384 x 36 x 2, 32,768 x 36 x 2 and 65, 536 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
DESCRIPTION
The IDT72V3684/72V3694/72V36104 are designed to run off a 3.3V
supply for exceptionally low-power consumption. These devices are mono-
lithic, high-speed, low-power, CMOS bidirectional synchronous (clocked)
FIFO memory which supports clock frequencies up to 100 MHz and has read
access times as fast as 6.5ns. Two independent 16,384/32,768/65,536 x 36
dual-port SRAM FIFOs on board each chip buffer data in opposite directions.
FIFO data on Port B can be input and output in 36-bit, 18-bit, or 9-bit formats
with a choice of Big- or Little-Endian configurations.
These devices are a synchronous (clocked) FIFO, meaning each port
employs a synchronous interface. All data transfers through a port are gated
to the LOW-to-HIGH transition of a port clock by enable signals. The clocks for
each port are independent of one another and can be asynchronous or
coincident. The enables for each port are arranged to provide a simple
bidirectional interface between microprocessors and/or buses with synchro-
nous control.
Communication between each port may bypass the FIFOs via two mailbox
registers. The mailbox registers’ width matches the selected Port B bus width.
PIN CONFIGURATION
CSA
FFA/IRA
EFA/ORA
PRS1 RT1
Vcc
AFA
AEA
MBF2
MBA
MRS1
FS0/SD
GND
GND
FS1/SEN
MRS2
MBB
MBF1
Vcc
AEB
AFB
EFB/ORB
FFB/IRB
GND
CSB
W/RB
ENB
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
INDEX
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
W/RA
ENA
CLKA
GND
A35
A34
A33
A32
Vcc
A31
A30
GND
A29
A28
A27
A26
A25
A24
A23
BE/FWFT
GND
A22
Vcc
A21
A20
A19
A18
GND
A17
A16
A15
A14
A13
Vcc
A12
GND
A11
A10
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
CLKB
PRS2/RT2
Vcc
B35
B34
B33
B32
RTM
GND
B31
B30
B29
B28
B27
B26
Vcc
B25
B24
BM
GND
B23
B22
B21
B20
B19
B18
GND
B17
B16
SIZE
Vcc
B15
B14
B13
B12
GND
B11
B10
A9
A8
A7
A6
GND
A5
A4
A3
FS2
Vcc
A2
A1
A0
GND
B0
B1
B2
B3
B4
B5
GND
B6
Vcc
B7
B8
B9
4677 drw02
TQFP (PK128-1, order code: PF)
TOP VIEW
2
IDT72V3684/72V3694/72V36104 3.3V CMOS SyncBiFIFO
TM
WITH
BUS-MATCHING 16,384 x 36 x 2, 32,768 x 36 x 2, 65 and 536 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
Each Mailbox register has a flag (MBF1 and
MBF2)
to signal when new mail
has been stored.
Two kinds of reset are available on these FIFOs: Master Reset and Partial
Reset. Master Reset initializes the read and write pointers to the first location
of the memory array, configures the FIFO for Big- or Little-Endian byte
arrangement and selects serial flag programming, parallel flag programming,
or one of five possible default flag offset settings, 8, 16, 64, 256 or 1,024. There
are two Master Reset pins,
MRS1
and
MRS2.
Partial Reset also sets the read and write pointers to the first location of the
memory. Unlike Master Reset, any settings existing prior to Partial Reset (i.e.,
programming method and partial flag default offsets) are retained. Partial Reset
is useful since it permits flushing of the FIFO memory without changing any
configuration settings. Each FIFO has its own, independent Partial Reset pin,
PRS1
and
PRS2.
Both FIFO's have Retransmit capability, when a Retransmit is performed on
a respective FIFO only the read pointer is reset to the first memory location. A
Retransmit is performed by using the Retransmit Mode, RTM pin in conjunction
with the Retransmit pins
RT1
or
RT2,
for each respective FIFO. Note that the
two Retransmit pins
RT1
and
RT2
are muxed with the Partial Reset pins.
These devices have two modes of operation: In the
IDT Standard mode,
the
first word written to an empty FIFO is deposited into the memory array. A read
operation is required to access that word (along with all other words residing
in memory). In the
First Word Fall Through mode
(FWFT), the first long-word
(36-bit wide) written to an empty FIFO appears automatically on the outputs, no
read operation is required (Nevertheless, accessing subsequent words does
necessitate a formal read request). The state of the BE/FWFT pin during FIFO
operation determines the mode in use.
Each FIFO has a combined Empty/Output Ready Flag (EFA/ORA and
EFB/
ORB) and a combined Full/Input Ready Flag (FFA/IRA and
FFB/IRB).
The
EF
and
FF
functions are selected in the IDT Standard mode.
EF
indicates
whether or not the FIFO memory is empty.
FF
shows whether the memory is
full or not. The IR and OR functions are selected in the First Word Fall Through
mode. IR indicates whether or not the FIFO has available memory locations.
OR shows whether the FIFO has data available for reading or not. It marks the
presence of valid data on the outputs.
Each FIFO has a programmable Almost-Empty flag (AEA and
AEB)
and a
programmable Almost-Full flag (AFA and
AFB). AEA
and
AEB
indicate when
a selected number of words remain in the FIFO memory.
AFA
and
AFB
indicate
when the FIFO contains more than a selected number of words.
FFA/IRA, FFB/IRB, AFA
and
AFB
are two-stage synchronized to the port
clock that writes data into its array.
EFA/ORA, EFB/ORB, AEA
and
AEB
are
two-stage synchronized to the port clock that reads data from its array.
Programmable offsets for
AEA, AEB, AFA
and
AFB
are loaded in parallel using
Port A or in serial via the SD input. Five default offset settings are also provided.
The
AEA
and
AEB
threshold can be set at 8, 16, 64, 256 or 1,024 locations
from the empty boundary and the
AFA
and
AFB
threshold can be set at 8, 16,
64, 256 or 1,024 locations from the full boundary. All these choices are made
using the FS0, FS1 and FS2 inputs during Master Reset.
Interspersed Parity can also be selected during a Master Reset of the FIFO.
If Interspersed Parity is selected then during parallel programming of the flag
offset values, the device will ignore data line A8. If Non-Interspersed Parity is
selected then data line A8 will become a valid bit.
Two or more devices may be used in parallel to create wider data paths. If,
at any time, the FIFO is not actively performing a function, the chip will
automatically power down. During the power down state, supply current
consumption (I
CC
) is at a minimum. Initiating any operation (by activating control
inputs) will immediately take the device out of the power down state.
The IDT72V3684/72V3694/72V36104 are characterized for operation
from 0°C to 70°C. Industrial temperature range (-40°C to +85°C) is available.
They are fabricated using IDT’s high speed, submicron CMOS technology.
3
IDT72V3684/72V3694/72V36104 3.3V CMOS SyncBiFIFO
TM
WITH
BUS-MATCHING 16,384 x 36 x 2, 32,768 x 36 x 2 and 65, 536 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTIONS
Symbol
A0-A35
AEA
AEB
AFA
AFB
B0-B35
BE/FWFT
Name
Port A Data
Port A Almost-
Empty Flag
Port B Almost-
Empty Flag
Port A Almost-
Full Flag
Port B Almost-
Full Flag
Port A Data
Big-Endian/
First Word
Fall Through
Select
I/O
I/O
O
O
O
O
I/O
I
36-bit bidirectional data port for side A.
Programmable Almost-Empty flag synchronized to CLKA. It is LOW when the number of words in
FIFO2 is less than or equal to the value in the Almost-Empty A Offset register, X2.
Programmable Almost-Empty flag synchronized to CLKB. It is LOW when the number of words in
FIFO1 is less than or equal to the value in the Almost-Empty B Offset register, X1.
Programmable Almost-Full flag synchronized to CLKA. It is LOW when the number of empty locations
in FIFO1 is less than or equal to the value in the Almost-Full A Offset register, Y1.
Programmable Almost-Full flag synchronized to CLKB. It is LOW when the number of empty
locations in FIFO2 is less than or equal to the value in the Almost-Full B Offset register, Y2.
36-bit bidirectional data port for side B.
This is a dual purpose pin. During Master Reset, a HIGH on BE will select Big Endian operation. In
this case, depending on the bus size, the most significant byte or word on Port A is read from Port B
first (A-to-B data flow) or written to Port B first (B-to-A data flow). A LOW on BE will select Little-Endian
operation. In this case, the least significant byte or word on Port A is read from Port B first (for A-to-B data
flow) or written to Port B first (B-to-A data flow). After Master Reset, this pin selects the timing mode. A
HIGH on
FWFT
selects IDT Standard mode, a LOW selects First Word Fall Through mode. Once the
timing mode has been selected, the level on
FWFT
must be static throughout device operation.
A HIGH on this pin enables either byte or word bus width on Port B, depending on the state of SIZE.
A LOW selects long word operation. BM works with SIZE and BE to select the bus size and endian
arrangement for Port B. The level of BM must be static throughout device operation.
CLKA is a continuous clock that synchronizes all data transfers through Port A and can be
asynchronous or coincident to CLKB.
FFA/IRA, EFA/ORA, AFA,
and
AEA
are all synchronized to the
LOW-to-HIGH transition of CLKA.
CLKB is a continuous clock that synchronizes all data transfers through Port B and can be
asynchronous or coincident to CLKA.
FFB/IRB, EFB/ORB, AFB,
and
AEB
are synchronized to the
LOW-to-HIGH transition of CLKB.
CSA
must be LOW to enable to LOW-to-HIGH transition of CLKA to read or write on Port A. The A0-A35
outputs are in the high-impedance state when
CSA
is HIGH.
CSB
must be LOW to enable a LOW-to-HIGH transition of CLKB to read or write data on Port B. The
B0-B35 outputs are in the high-impedance state when
CSB
is HIGH.
This is a dual function pin. In the IDT Standard mode, the
EFA
function is selected.
EFA
indicates whether or not the FIFO2 memory is empty. In the FWFT mode, the ORA function is
selected. ORA indicates the presence of valid data on A0-A35 outputs, available for reading.
EFA/ORA
is synchronized to the LOW-to-HIGH transition of CLKA.
This is a dual function pin. In the IDT Standard mode, the
EFB
function is selected.
EFB
indicates
whether or not the FIFO1 memory is empty. In the FWFT mode, the ORB function is selected. ORB
indicates the presence of valid data on the B0-B35 outputs, available for reading.
EFB/ORB
is
synchronized to the LOW-to-HIGH transition of CLKB.
ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data on Port A.
ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data on Port B.
This is a dual function pin. In the IDT Standard mode, the
FFA
function is selected.
FFA
indicates
whether or not the FIFO1 memory is full. In the FWFT mode, the IRA function is selected. IRA
indicates whether or not there is space available for writing to the FIFO1 memory.
FFA/IRA
is
synchronized to the LOW-to-HIGH transition of CLKA.
This is a dual function pin. In the IDT Standard mode, the
FFB
function is selected.
FFB
indicates
whether or not the FIFO2 memory is full. In the FWFT mode, the IRB function is selected. IRB
indicates whether or not there is space available for writing to the FIFO2 memory.
FFB/IRB
is
synchronized to the LOW-to-HIGH transition of CLKB.
Description
BM
(1)
Bus-Match Select
(Port B)
Port A Clock
I
CLKA
I
CLKB
Port B Clock
I
CSA
CSB
EFA/ORA
Port A Chip Select
Port B Chip Select
Port A Empty/
Output Ready Flag
I
I
O
EFB/ORB
Port B Empty/
Output Ready Flag
O
ENA
ENB
FFA/IRA
Port A Enable
Port B Enable
Port A Full/
Input Ready Flag
I
I
O
FFB/IRB
Port B Full/
Input Ready Flag
O
4
IDT72V3684/72V3694/72V36104 3.3V CMOS SyncBiFIFO
TM
WITH
BUS-MATCHING 16,384 x 36 x 2, 32,768 x 36 x 2, 65 and 536 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTIONS (CONTINUED)
Symbol
FS0/SD
Name
I/O
Description
Flag Offset Select 0/ I FS1/SEN and FS0/SD are dual-purpose inputs used for flag offset register programming. During Master
Serial Data
Reset, FS1/SEN and FS0/SD, together with FS2, select the flag offset programming method. Three offset
register programming methods are available: automatically load one of five preset values (8, 16, 64, 256 or
1,024), parallel load from Port A, and serial load.
FS1/SEN Flag Offset Select 1/ I
Serial Enable,
When serial load is selected for flag offset register programming, FS1/SEN is used as an enable
synchronous to the LOW-to-HIGH transition of CLKA. When FS1/SEN is LOW, a rising edge on CLKA load
(1)
FS2
Flag Offset Select 2
I the bit present on FS0/SD into the X and Y registers. The number of bit writes required to program the offset
registers is 56 for the IDT72V3684, 60 for the IDT72V3694, and 64 for the IDT72V36104. The first bit write
stores the Y- register (Y1) MSB and the last bit write stores the X-register (X2) LSB.
MBA
Port A Mailbox
I A HIGH level on MBA chooses a mailbox register for a Port A read or write operation. When the A0-A35
Select
outputs are active, a HIGH level on MBA selects data from the mail2 register for output and a LOW level
selects FIFO2 output register data for output.
MBB
Port B Mailbox
Select
Mail1 Register
Flag
Mail2 Register
Flag
FIFO1 Master
Reset
I
A HIGH level on MBB chooses a mailbox register for a Port B read or write operation. When the B0-B35
outputs are active, a HIGH level on MBB selects data from the mail1 register for output and a LOW level
selects FIFO1 output register data for output.
MBF1
is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the mail1 register. Writes to the mail1
register are inhibited while
MBF1
is LOW.
MBF1
is set HIGH by a LOW-to-HIGH transition of CLKB when a
Port B read is selected and MBB is HIGH.
MBF1
is set HIGH following either a Master or Partial Reset of FIFO1.
MBF2
is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the mail2 register. Writes to the mail2
register are inhibited while
MBF2
is LOW.
MBF2
is set HIGH by a LOW-to-HIGH transition of CLKA when a Port
A read is selected and MBA is HIGH.
MBF2
is set HIGH following either a Master or Partial Reset of FIFO2.
A LOW on this pin initializes the FIFO1 read and write pointers to the first location of memory and sets the Port
B output register to all zeroes. A LOW-to-HIGH transition on
MRS1
selects the programming method (serial or parallel)
and one of five programmable flag default offsets for FIFO1 and FIFO2. It also configures Port B for bus size and
endian arrangement. Four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB must
occur while
MRS1
is LOW.
A LOW on this pin initializes the FIFO2 read and write pointers to the first location of memory and sets the Port A
output register to all zeroes. A LOW-to-HIGH transition on
MRS2,
toggled simultaneously with
MRS1,
selects the
programming method (serial or parallel) and one of the programmable flag default offsets for FIFO2. Four LOW-to-
HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB must occur while
MRS2
is LOW.
This pin is muxed for both Partial Reset and Retransmit operations, it is used in conjunction with the RTM pin.
If RTM is in a LOW condition, a LOW on this pin performs a Partial Reset on FIFO1 and initializes the FIFO1 read
and write pointers to the first location of memory and sets the Port B output register to all zeroes. During Partial Reset,
the currently selected bus size, endian arrangement, programming method (serial or parallel), and programmable
flag settings are all retained. If RTM is HIGH, a LOW on this pin performs a Retransmit and initializes the FIFO1 read
pointer only to the first memory location.
This pin is muxed for both Partial Reset and Retransmit operations, it is used in conjunction with the RTM pin.
If RTM is in a LOW condition, a LOW on this pin performs a Partial Reset on FIFO2 and initializes the FIFO2 read
and write selected bus size, endian arrangement, programming method (serial or parallel), and programmable flag
settings are all retained. If RTM is HIGH, a LOW on this pin performs a Retransmit and initializes the FIFO2 read pointer
only to the first memory location.
This pin is used in conjunction with the
RT1
and
RT2
pins. When RTM is HIGH a Retransmit is performed on
FIFO1 or FIFO2 respectively.
A HIGH on this pin when BM is HIGH selects byte bus (9-bit) size on Port B. A LOW on this pin when BM is HIGH
selects word (18-bit) bus size. SIZE works with BM and BE to select the bus size and endian arrangement for Port
B. The level of SIZE must be static throughout device operation
A HIGH selects a write operation and a LOW selects a read operation on Port A for a LOW-to-HIGH
transition of CLKA. The A0-A35 outputs are in the HIGH impedance state when W/RA is HIGH.
A LOW selects a write operation and a HIGH selects a read operation on Port B for a LOW-to-HIGH
transition of CLKB. The B0-B35 outputs are in the HIGH impedance state when
W/RB
is LOW.
MBF1
O
MBF2
O
MRS1
I
MRS2
FIFO2 Master
Reset
I
PRS1/
RT1
Partial Reset/
Retransmit FIFO1
I
PRS2/
RT2
Partial Reset/
Retransmit FIFO2
I
RTM
SIZE
(1)
Retransmit Mode
Bus Size Select
I
I
W/RA
W/RB
Port-A Write/
Read Select
Port-B Write/
Read Select
I
I
NOTE:
1. FS2, BM and SIZE inputs are not TTL compatible. These inputs should be tied to GND or V
CC
.
5
FPGA/CPLD
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