IDT54/74FCT574T/AT/CT
FAST CMOS OCTAL D REGISTERS (3-STATE)
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
FAST CMOS OCTAL D
REGISTERS (3-STATE)
IDT54/74FCT574T/AT/CT
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•
•
•
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FEATURES:
Std., A, and C grades
Low input and output leakage
≤
1µA (max.)
CMOS power levels
True TTL input and output compatibility:
– V
OH
= 3.3V (typ.)
– V
OL
= 0.3V (typ.)
High Drive outputs (-15mA I
OH
, 48mA I
OL
)
Meets or exceeds JEDEC standard 18 specifications
Military product compliant to MIL-STD-883, Class B and DESC
listed (dual marked)
Power off disable outputs permit "live insertion"
Available in the following packages:
– Industrial: SOIC, QSOP
– Military: CERDIP, LCC
DESCRIPTION:
The FCT574T is an 8-bit register built using an advanced dual metal
CMOS technology. These registers consist of eight D-type flip-flops with a
buffered common clock and buffered 3-state output control. When the output
enable (OE) input is low, the eight outputs are enabled. When the
OE
input
is high, the outputs are in the high-impedance state.
Input data meeting the set-up and hold time requirements of the D inputs
is transferred to the Q outputs on the low-to-high transition of the clock input.
FUNCTIONAL BLOCK DIAGRAM
D
0
CP
CP D
Q
D
1
D
2
D
3
D
4
D
5
D
6
D
7
CP D
Q
CP
D
Q
CP
D
Q
CP
D
Q
CP
D
Q
CP
D
Q
CP
D
Q
OE
Q
0
Q
1
Q
2
Q
3
Q
4
Q
5
Q
6
Q
7
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
1
NOVEMBER 2016
DSC-5494/7
IDT54/74FCT574T/AT/CT
FAST CMOS OCTAL D REGISTERS (3-STATE)
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
PIN CONFIGURATION
OE
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
GND
2
3
4
5
6
7
8
9
10
19
18
17
16
15
14
13
12
11
Q
0
Q
1
Q
2
Q
3
Q
4
Q
5
Q
6
Q
7
CP
3
2
1
20
19
18
17
16
15
14
9
10
11
12
13
D
1
1
D
0
20
Q
0
V
CC
OE
INDEX
V
CC
D
2
D
3
D
4
D
5
D
6
4
5
6
7
8
Q
1
Q
2
Q
3
Q
4
Q
5
Q
7
CERDIP/ SOIC/ TSSOP
TOP VIEW
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
(2)
V
TERM
(3)
T
STG
I
OUT
Description
Terminal Voltage with Respect to GND
Terminal Voltage with Respect to GND
Storage Temperature
DC Output Current
Max
–0.5 to +7
–0.5 to V
CC
+0.5
–65 to +150
–60 to +120
Unit
V
V
°C
mA
PIN DESCRIPTION
Pin Names
Dx
CP
Qx
Q
x
OE
Description
D flip-flop data inputs
Clock Pulse for the register. Enters data on LOW-to-
HIGH transition.
3-State Outputs (TRUE)
3-State Outputs (INVERTED)
Active LOW 3-State Output Enable Input
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage may exceed
Vcc by +0.5V unless otherwise noted.
2. Inputs and Vcc terminals only.
3. Output and I/O terminals only.
FUNCTION TABLE
(1)
Function
High-Z
Load
Register
OE
H
H
L
L
H
H
Inputs
CP
L
H
↑
↑
↑
↑
Dx
X
X
L
H
L
H
Outputs
Qx
Z
Z
L
H
Z
Z
Internal
Qx
NC
NC
H
L
H
L
CAPACITANCE
(T
A
= +25°C, F = 1.0MHz)
Symbol
C
IN
C
OUT
Parameter
(1)
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Typ.
6
8
Max.
10
12
Unit
pF
pF
NOTE:
1. This parameter is measured at characterization but not tested.
NOTE:
1. H = HIGH Voltage Level
X = Don’t Care
L = LOW Voltage Level
Z = High Impedance
NC = No Change
↑
= LOW-to-HIGH transition
2
GND
LCC
TOP VIEW
CP
Q
6
D
7
IDT54/74FCT574T/AT/CT
FAST CMOS OCTAL D REGISTERS (3-STATE)
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: T
A
= –40°C to +85°C, V
CC
= 5.0V ±5%; Military: T
A
= –55°C to +125°C, V
CC
= 5.0V ±10%
Symbol
V
IH
V
IL
I
IH
I
IL
I
OZH
I
OZL
I
I
V
IK
V
H
I
CC
Parameter
Input HIGH Level
Input LOW Level
Input HIGH Current
(4)
Input LOW Current
(4)
High Impedance Output Current
(3-State output pins)
(4)
Input HIGH Current
(4)
Clamp Diode Voltage
Input Hysteresis
Quiescent Power Supply Current
V
CC
= Max., V
I
= V
CC
(Max.)
V
CC
= Min, I
IN
= -18mA
—
V
CC
= Max., V
IN
= GND or V
CC
Test Conditions
(1)
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
V
CC
= Max.
V
CC
= Max.
V
CC
= Max
V
I
= 2.7V
V
I
= 0.5V
V
O
= 2.7V
V
O
= 0.5V
Min.
2
—
—
—
—
—
—
—
—
—
Typ.
(2)
—
—
—
—
—
—
—
–0.7
200
0.01
Max.
—
0.8
±1
±1
±1
±1
±1
–1.2
—
1
µA
V
mV
mA
Unit
V
V
µA
µA
µA
OUTPUT DRIVE CHARACTERISTICS
Symbol
V
OH
Parameter
Output HIGH Voltage
Test Conditions
(1)
V
CC
= Min
I
OH
= –6mA MIL
V
IN
= V
IH
or V
IL
I
OH
= –8mA IND
I
OH
= –12mA MIL
I
OH
= –15mA IND
V
CC
= Min
I
OL
= 32mA MIL
V
IN
= V
IH
or V
IL
I
OL
= 48mA IND
V
CC
= Max., V
O
= GND
(3)
Min.
2.4
2
—
–60
Typ.
(2)
3.3
3
0.3
–120
Max.
—
—
0.5
–225
V
mA
Unit
V
V
OL
I
OS
Output LOW Voltage
Short Circuit Current
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. The test limit for this parameter is ±5µA at T
A
= –55°C.
3
IDT54/74FCT574T/AT/CT
FAST CMOS OCTAL D REGISTERS (3-STATE)
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Symbol
ΔI
CC
I
CCD
Parameter
Quiescent Power Supply Current
TTL Inputs HIGH
Dynamic Power Supply
Current
(4)
V
CC
= Max.
V
IN
= 3.4V
(3)
V
CC
= Max.
Outputs Open
OE
= GND
One Input Toggling
50% Duty Cycle
V
CC
= Max.
Outputs Open
f
CP
= 10MHz
50% Duty Cycle
OE
= GND
fi = 5MHz
One Bit Toggling
V
CC
= Max.
Outputs Open
f
CP
= 10MHz
50% Duty Cycle
OE
= GND
Eight Bits Toggling
fi = 2.5MHz
V
IN
= V
CC
V
IN
= GND
Test Conditions
(1)
Min.
—
—
Typ.
(2)
0.5
0.15
Max.
2
0.25
Unit
mA
mA/
MHz
I
C
Total Power Supply Current
(6)
V
IN
= V
CC
V
IN
= GND
V
IN
= 3.4V
V
IN
= GND
—
—
1.5
2
3.5
5.5
mA
V
IN
= V
CC
V
IN
= GND
V
IN
= 3.4V
V
IN
= GND
—
—
3.8
6
7.3
(5)
16.3
(5)
mA
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25°C ambient.
3. Per TTL driven input; (V
IN
= 3.4V). All other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of
ΔI
CC
formula. These limits are guaranteed but not tested.
6. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
ΔI
CC
D
H
N
T
+ I
CCD
(f
CP
/2+ f
i
N
i
)
I
CC
= Quiescent Current
ΔI
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current caused by an Input Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for Register Devices (Zero for Non-Register Devices)
f
i
= Output Frequency
N
i
= Number of Outputs at f
i
All currents are in milliamps and all frequencies are in megahertz.
4
IDT54/74FCT574T/AT/CT
FAST CMOS OCTAL D REGISTERS (3-STATE)
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE - INDUSTRIAL
FCT574AT
Symbol
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
SU
t
H
t
W
Set-up Time, HIGH or LOW
Dx to CP
Hold Time, HIGH or LOW
Dx to CP
CP Pulse Width HIGH or LOW
(3)
5
—
5
—
ns
1.5
—
1.5
—
ns
2
—
2
—
ns
Output Disable Time
1.5
5.5
1.5
5
ns
Parameter
Propagation Delay
CP to Qx
Output Enable Time
Condition
(1)
C
L
= 50pF
R
L
= 500Ω
1.5
6.5
1.5
5.5
ns
Min
.
(2)
2
Max.
6.5
2
FCT574CT
Min
.
(2)
Max.
5.2
Unit
ns
SWITCHING CHARACTERISTICS OVER OPERATING RANGE - MILITARY
FCT574T
Symbol
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
SU
t
H
t
W
Set-up Time, HIGH or LOW
Dx to CP
Hold Time, HIGH or LOW
Dx to CP
CP Pulse Width HIGH or LOW
(3)
7
—
6
—
6
—
ns
1.5
—
1.5
—
1.5
—
ns
2
—
2
—
2
—
ns
Output Disable Time
1.5
8
1.5
6.5
1.5
5.7
ns
Parameter
Propagation Delay
CP to Qx
Output Enable Time
Condition
(1)
C
L
= 50pF
R
L
= 500Ω
1.5
14
1.5
7.5
1.5
6.2
ns
Min
.
(2)
2
Max.
11
FCT574AT
Min
.
(2)
2
Max.
7.2
FCT574CT
Min
.
(2)
2
Max.
6.2
Unit
ns
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This limit is guaranteed but not tested.
5
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