PRELIMINARY
CYF2144V
144-Mbit Programmable
Multi-Queue FIFOs
144-Mbit Programmable Multi-Queue FIFOs
Features
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Functional Description
The Cypress programmable FIFO family offers the industry’s
highest-density programmable FIFO memory device. It has
independent read and write ports, which can be clocked up to
100 MHz. User can configure input and output bus sizes. The
maximum bus size of 36 bits enables a maximum data
throughput of 3.6 Gbps. The read and write ports can support
multiple I/O voltage standards. The user-programmable
registers enable user to configure the device operation as
desired. The device also offers a simple and easy-to-use
interface to reduce implementation and debugging efforts,
improve time-to-market, and reduce engineering costs. This
makes it an ideal memory choice for a wide range of applications
including multiprocessor interfaces, video and image
processing, networking and telecommunications, high-speed
data acquisition, or any system that needs buffering at very high
speeds across different clock domains.
As implied by the name, the functionality of the FIFO is such that
the data is read out of the read port in the same sequence in
which it was written into the write port. The data is sequentially
written into the FIFO from the write port. If the writes and inputs
are enabled, the data on the write port gets written into the device
at the rising edge of the write clock. Enabling the reads and
outputs fetches data on the read port at every rising edge of the
read clock. Both reads and writes can occur simultaneously at
different speeds provided the ratio of read to write clock is in the
range of 0.5 to 2. Appropriate flags are set whenever the FIFO
is empty or full.
The device also supports multi-queue operation upto 8 queues,
mark and retransmit of data, and a flow-through mailbox register.
All descriptions are given assuming the device CYF2144V is
operated in × 36 mode. They hold good for all port sizes × 9,
× 12, × 16, × 18, × 20, × 24 and × 32 unless otherwise specified.
The only difference will be in the input and output bus width.
Table 1 on page 8
shows the part of bus with valid data from
D[35:0] and Q[35:0] in × 9, × 12, × 16, × 18, × 20, × 24, × 32 and
× 36 modes.
Memory organization
❐
Industry’s largest first in first out (FIFO) memory densities:
144-Mbit
❐
Selectable memory organization: × 9, × 12, × 16, × 18, × 20,
× 24, × 32, × 36
Up to 100-MHz clock operation
Unidirectional operation
Independent read and write ports
❐
Supports simultaneous read and write operations
❐
Reads and writes operate on independent clocks, upto a
maximum ratio of two, enabling data buffering across clock
domains.
❐
Supports multiple I/O voltage standard: Low voltage
complementary metal oxide semiconductor (LVCMOS) 3.3 V
and 1.8 V voltage standards.
Input and output enable control for write mask and read skip
operations
User configured multi-queue operating mode upto 8-queues
Mark and retransmit: resets read pointer to user marked
position
Empty and full flags
Flow-through mailbox register to send data from input to output
port, bypassing the FIFO sequence
Separate serial clock (SCLK) input for serial programming
Master reset to clear entire FIFO
Joint test action group (JTAG) port provided for boundary scan
function
Industrial temperature range: –40 °C to +85 °C
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Cypress Semiconductor Corporation
Document Number: 001-82371 Rev. *A
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised November 7, 2012
PRELIMINARY
CYF2144V
Logic Block Diagram
D[35:0]
IE
WEN
WCLK
LD
SPI_SEN SPI_SCLK
INPUT
REGISTER
WQSEL[2:0]
CONFIGURATION
REGISTERS/MAILBOX
SPI_SI
MB
WRITE
CONTROL LOGIC
FF
EF
Qval[2:0]
WRITE POINTER
Memory Array
MRS
FLAG LOGIC
144-Mbit
RESET POINTER
READ POINTER
DVal
TCK
TRST
TMS
TDO
TDI
JTAG CONTROL
READ CONTROL
LOGIC
OUTPUT
REGISTER
MARK, RT
RQSEL[2:0]
RCLK
REN
OE
MEMORY LOGIC
ORGANIZATION
Q[35:0]
PORTSZ[2:0]
Document Number: 001-82371 Rev. *A
Page 2 of 31
PRELIMINARY
CYF2144V
Contents
Pin Diagram for CYF2XXXVXXL ...................................... 4
Pin Definitions .................................................................. 5
Architecture ...................................................................... 7
Reset Logic ................................................................. 7
Flag Operation ............................................................. 7
Full Flag ....................................................................... 7
Empty Flag .................................................................. 7
Retransmit from Mark Operation ................................. 7
Flow-through mailbox Register .................................... 7
Selecting Word Sizes .................................................. 7
Data Valid Signal (DVal) .............................................. 8
Queue Valid Signal (QVal[2:0]) ................................... 8
Power Up ........................................................................... 8
Write Mask and Read Skip Operation ......................... 9
Multi-Queue Operation ................................................ 9
Width Expansion Configuration ................................. 11
Memory Organization for Different Port Sizes ........... 11
Read/Write Clock Requirements ............................... 12
JTAG operation ............................................................... 13
Maximum Ratings ........................................................... 14
Operating Range ............................................................. 14
Recommended DC Operating Conditions .................... 14
Electrical Characteristics ............................................... 14
I/O Characteristics .......................................................... 15
Latency Table .................................................................. 15
AC Test Load Conditions ............................................... 16
Switching Characteristics .............................................. 17
Switching Waveforms .................................................... 18
Ordering Information ...................................................... 27
Ordering Code Definitions ......................................... 27
Package Diagram ............................................................ 28
Acronyms ........................................................................ 29
Document Conventions ................................................. 29
Units of Measure ....................................................... 29
Document History Page ................................................. 30
Sales, Solutions, and Legal Information ...................... 31
Worldwide Sales and Design Support ....................... 31
Products .................................................................... 31
PSoC Solutions ......................................................... 31
Document Number: 001-82371 Rev. *A
Page 3 of 31
PRELIMINARY
CYF2144V
Pin Diagram for CYF2XXXVXXL
Figure 1. 209-ball FBGA (Top View)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
FF
EF
D4
D6
D8
D10
D12
D14
D16
DNU
D18
D20
D22
D24
D26
D28
DVal
QVal1
TDO
2
D0
D2
D5
D7
D9
D11
D13
D15
D17
DNU
D19
D21
D23
D25
D27
D29
DNU
QVal0
QVal2
3
D1
D3
WEN
V
SS
V
CC2
V
SS
V
CC2
V
SS
V
CC2
WCLK
V
CC2
V
SS
V
CC2
V
SS
V
CC2
V
SS
D30
D32
D34
4
WQSEL0
WQSEL1
WQSEL2
V
CC1
V
CC2
V
SS
V
CC2
V
SS
V
CC2
DNU
V
CC2
V
SS
V
CC2
V
SS
V
CC2
V
CC1
D31
D33
D35
5
PORTSZ0
DNU
V
CC1
DNU
V
CCIO
V
SS
V
CCIO
V
SS
V
CCIO
V
SS
V
CCIO
V
SS
V
CCIO
V
SS
V
CCIO
V
CC1
DNU
DNU
TDI
6
PORTSZ1
PORTSZ2
DNU
LD
V
CCIO
DNU
V
CC1
V
CC1
V
CC1
IE
V
CC1
V
CC1
V
CC1
SPI_SEN
V
CCIO
SPI_SI
DNU
[1]
MRS
TRST
7
DNU
DNU
V
CC1
DNU
V
CCIO
V
SS
V
CCIO
V
SS
V
CCIO
VSS
V
CCIO
VSS
V
CCIO
V
SS
V
CCIO
V
CC1
SPI_SCLK
MB
TMS
8
RQSEL0
RQSEL1
RQSEL2
V
CC1
V
CC2
V
SS
V
CC2
V
SS
V
CC2
DNU
V
CC2
VSS
V
CC2
V
SS
V
CC2
V
CC1
V
REF
DNU
TCK
9
RT
REN
RCLK
V
SS
V
CC2
V
SS
V
CC2
V
SS
V
CC2
V
CCIO
V
CC2
V
SS
V
CC2
V
SS
V
CC2
V
SS
OE
MARK
DNU
10
Q0
Q2
Q4
Q6
Q8
Q10
Q12
Q14
Q16
V
CCIO
Q18
Q20
Q22
Q24
Q26
Q28
Q30
Q32
Q34
11
Q1
Q3
Q5
Q7
Q9
Q11
Q13
Q15
Q17
V
CCIO
Q19
Q21
Q23
Q25
Q27
Q29
Q31
Q33
Q35
Note
1. This pin should be tied to V
SS
preferably or can be left floating to ensure normal operation.
Document Number: 001-82371 Rev. *A
Page 4 of 31
PRELIMINARY
CYF2144V
Pin Definitions
Pin Name
D[35:0]
Q[35:0]
WEN
REN
IE
I/O
Input
Output
Input
Input
Input
Data inputs: Data inputs for a 36-bit bus.
Data outputs: Data outputs for a 36-bit bus.
Write enable: WEN enables WCLK to write data into the FIFO memory and configuration registers.
Read enable: REN enables RCLK to read data from the FIFO memory and configuration registers.
Input enable: IE is the data input enable signal that controls the enabling and disabling of the 36-bit data
input pins. If it is enabled, data on the D[35:0] pins is written into the FIFO. The internal write address
pointer is always incremented at rising edge of WCLK if WEN is enabled, regardless of the IE level. This
is used for ‘write masking’ or incrementing the write pointer without writing into a location.
Output enable: When OE is LOW, FIFO data outputs are enabled; when OE is HIGH, the FIFO’s outputs
are in High Z (high impedance) state.
Write clock: When enabled by WEN, the rising edge of WCLK writes data into the FIFO if LD is high and
into the configuration registers if LD is low.
Read clock: When enabled by REN, the rising edge of RCLK reads data from the FIFO memory if LD is
high and from the configuration registers if LD is low.
Empty flag: When EF is LOW, the Queue is empty. EF is synchronized to RCLK.
Full flag: When FF is LOW, the Queue is full. FF is synchronized to WCLK.
Load: When LD is LOW, D[7:0] (Q[7:0]) are written (read) into (from) the configuration registers. When
LD is HIGH, D[35:0] (Q[35:0]) are written (read) into (from) the FIFO.
Retransmit: A HIGH pulse on RT resets the internal read pointer to a physical location of the FIFO which
is marked by the user (using MARK pin). With every valid read cycle after retransmit, previously accessed
data is read and the read pointer is incremented until it is equal to the write pointer.
Master reset: MRS initializes the read and write pointers to zero and sets the output register to all zeroes.
During Master Reset, the configuration registers are all set to default values and the flags are reset.
Serial clock: A rising edge on SPI_SCLK clocks the serial data present on the SPI_SI input into the offset
registers if SPI_SEN is enabled.
Serial input: Serial input when SPI_SEN is enabled.
Serial enable: Enables serial loading of configuration registers.
Mark for retransmit: When this pin is asserted the current location of the read pointer is marked. Any
subsequent retransmit operation resets the read pointer to this position.
Mailbox: When asserted the reads and writes happen to flow-through mailbox register.
Write Queue select: Select maximum eight Queues using pins.
Read Queue select: Select maximum eight Queues using pins.
Test clock (TCK) pin for JTAG.
Reset pin for JTAG.
Test mode select (TMS) pin for JTAG.
Test data in (TDI) pin for JTAG.
Test data out (TDO) for JTAG.
Data valid: Active low data valid signal to indicate valid data on Q[35:0].
Pin Description
OE
WCLK
RCLK
EF
FF
LD
RT
Input
Input
Input
Output
Output
Input
Input
MRS
SPI_SCLK
SPI_SI
SPI_SEN
MARK
MB
WQSEL[2:0]
RQSEL[2:0]
TCK
TRST
TMS
TDI
TDO
DVal
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Output
Document Number: 001-82371 Rev. *A
Page 5 of 31
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