64K x 32
3.3V Synchronous SRAM
Flow-Through Outputs
Burst Counter, Single Cycle Deselect
Features
64K x 32 memory configuration
Supports high performance system speed
Commercial:
— 11 11ns Clock-to-Data Access (50 MHz)
Commercial and Industrial:
— 12 12ns Clock-to-Data Access (50 MHz)
Single-cycle deselect functionality (Compatible with
Micron Part # MT58LC64K32B2LG-XX)
LBO
input selects interleaved or linear burst mode
Self-timed write cycle with global write control (GW), byte
write enable (BWE), and byte writes (BWx)
Power down controlled by ZZ input
Single 3.3V power supply (+10/-5%)
Packaged in a JEDEC Standard 100-pin rectangular plastic
thin quad flatpack (TQFP).
IDT71V633
x
x
x
x
x
x
x
x
Description
The IDT71V633 is a 3.3V high-speed 2,097,152-bit (2-Mbit) SRAM
organized as 64K x 32 with full support of various processor interfaces
including the Pentium™ and PowerPC™. The flow-through burst archi-
tecture provides cost-effective 2-1-1-1 performance for processors up to
50 MHz.
The IDT71V633 SRAM contains write, data-input, address and control
registers. There are no registers in the data output path (flow-through
architecture). Internal logic allows the SRAM to generate a self-timed write
based upon a decision which can be left until the extreme end of the write
cycle.
The burst mode feature offers the highest level of performance to the
system designer, as the IDT71V633 can provide four cycles of data for
a single address presented to the SRAM. An internal burst address
counter accepts the first cycle address from the processor, initiating the
access sequence. The first cycle of output data will flow-through from the
array after a clock-to-data access time delay from the rising clock edge of
the same cycle. If burst mode operation is selected (ADV=LOW), the
subsequent three cycles of output data will be available to the user on the
next three rising clock edges. The order of these three addresses will be
defined by the internal burst counter and the
LBO
input pin.
The IDT71V633 SRAM utilizes IDT's high-performance 3.3V CMOS
process, and is packaged in a JEDEC Standard 14mm x 20mm 100-pin
thin plastic quad flatpack (TQFP).
Pin Description
A
0
–A
15
CE
CS
0
,
CS
1
OE
GW
BWE
BW
1
–BW
4
CLK
ADV
ADSC
ADSP
LBO
ZZ
I/O
0
–I/O
31
V
DD
, V
DDQ
V
SS
, V
SSQ
Address Inputs
Chip Enable
Chips Selects
Output Enable
Global Write Enable
Byte Write Enable
Individual Byte Write Selects
Clock Input
Burst Address Advance
Address Status (Cache Controller)
Address Status (Processor)
Linear / Interleaved Burst Order
Sleep Mode
Data Input/Output
Core and I/O Power Supply (3.3V)
Array Ground, I/O Ground
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
Power
Power
Synchronous
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Synchronous
Synchronous
Synchronous
DC
Asynchronous
Synchronous
N/A
N/A
3780 tbl 01
Pentium is a trademark of Intel Corp.
PowerPC is a trademark of International Business Machines, Inc.
AUGUST 2001
1
DSC-3780/05
©2000 Integrated Device Technology, Inc.
IDT71V633, 64K x 32, 3.3V Synchronous SRAM with
Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Pin Definitions
(1)
Symbol
A
0
–A
15
ADSC
Pin Function
Address Inputs
Address Status
(Cache Controller)
Address Status (Processor)
Burst Address Advance
I/O
I
I
Active
N/A
LOW
Description
Synchronous Address inputs. The address register is triggered by a combination of
the rising edge of CLK and
ADSC
Low or
ADSP
Low and
CE
Low.
Synchronous Address Status from Cache Controller.
ADSC
is an active LOW input
that is used to load the address registers with new addresses.
ADSC
is NOT gated
by
CE.
Synchronous Address Status from Processor.
ADSP
is an active LOW input that is
used to load the address registers with new addresses.
ADSP
is gated by
CE.
Synchronous Address Advance.
ADV
is an active LOW input that is used to advance
the internal burst counter, controlling burst access after the initial address is loaded.
When this input is HIGH the burst counter is not incremented; that is, there is no
address advance.
Synchronous byte write enable gates the byte write inputs
BW
1
–BW
4
. If
BWE
is
LOW at the rising edge of CLK then
BW
X
inputs are passed to the next stage in
the circuit. A byte write can still be blocked if
ADSP
is LOW at the rising edge of
CLK. If
ADSP
is HIGH and
BW
X
is LOW at the rising edge of CLK then data will
be written to the SRAM. If
BWE
is HIGH then the byte write inputs are blocked
and only
GW
can initiate a write cycle.
Synchronous byte write enables.
BW
1
controls I/O(7:0),
BW
2
controls I/O(15:8), etc.
Any active byte write causes all outputs to be disabled.
ADSP
LOW disables all byte
writes.
BW
1
–BW
4
must meet specified setup and hold tim es with respect to CLK.
Synchronous chip enable.
CE
is used with CS
0
and
CS
1
to enable the IDT71V633.
CE
also gates
ADSP.
This is the clock input. All timing references for the device are made with respect
to this input.
Synchronous active HIGH chip select. CS
0
is used with
CE
and
CS
1
to enable the
chip.
Synchronous active LOW chip select.
CS
1
is used with
CE
and CS
0
to enable the
chip.
Synchronous global write enable. This input will write all four 8-bit data bytes when
LOW on the rising edge of CLK.
GW
supercedes individual byte write enables.
Synchronous data input/output (I/O) pins. Only the data input path is registered and
triggered by the rising edge of CLK. Outputs are Flow-Through.
When
LBO
is HIGH the Interleaved Order (Intel) burst sequence is selected. When
LBO
is LOW the Linear (PowerPC) burst sequence is selected.
LBO
has an internal
pull-up resistor.
Asynchronous output enable. When
OE
is HIGH the I/O pins are in a high-impedence
state. When
OE
is LOW the data output drivers are enabled if the chip is also
selected.
3.3V core power supply inputs.
3.3V I/O power supply inputs.
Core ground pins.
I/O ground pins.
NC pins are not electrically connected to the chip.
Asynchronous sleep mode input. ZZ HIGH will gate the CLK internally and power
down the IDT71V633 to its lowest pow er consumption level. Data retention is
guaranteed in Sleep Mode. ZZ has an internal pull-down resistor.
3780 tbl 02
ADSP
ADV
I
I
LOW
LOW
BWE
Byte Write Enable
I
LOW
BW
1
–BW
4
Individual Byte Write
Enables
I
LOW
CE
CLK
CS
0
CS
1
GW
I/O
0
–I/O
31
LBO
Chip Enable
Clock
Chip Select 0
Chip Select 1
Global Write Enable
Data Input/Output
Linear Burst
I
I
I
I
I
I/O
I
LOW
N/A
HIGH
LOW
LOW
N/A
LOW
OE
Output Enable
I
LOW
V
DD
V
DDQ
V
SS
V
SSQ
NC
ZZ
Power Supply
Power Supply
Ground
Ground
No Connect
Sleep Mode
N/A
N/A
N/A
N/A
N/A
I
N/A
N/A
N/A
N/A
N/A
HIGH
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
2
IDT71V633, 64K x 32, 3.3V Synchronous SRAM with
Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Functional Block Diagram
LBO
ADV
CE
Burst
Sequence
INTERNAL
ADDRESS
CLK
ADSC
ADSP
CLK EN
ADDRESS
REGISTER
Byte 1
Write Register
Binary
Counter
CLR
2
Burst
Logic
16
A
0
*
A
1
*
Q0
Q1
64K x 32
BIT
MEMORY
ARRAY
2
16
A
0
, A
1
A
0
–A
15
GW
BWE
BW
1
A
2
–A
15
32
32
Byte 1
Write Driver
Byte 2
Write Register
8
Byte 2
Write Driver
BW
2
Byte 3
Write Register
8
Byte 3
Write Driver
BW
3
Byte 4
Write Register
8
Byte 4
Write Driver
BW
4
8
CE
CS
0
CS
1
D
Q
Enable
Register
DATA INPUT
REGISTER
CLK EN
ZZ
OE
32
Powerdown
OE
OUTPUT
BUFFER
.
I/O
0
–I/O
31
3780 drw 01
3
6.42
IDT71V633, 64K x 32, 3.3V Synchronous SRAM with
Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Absolute Maximum DC Ratings
(1)
Symbol
V
TERM
(2)
V
TERM
(3)
T
A
T
BIAS
T
STG
P
T
I
OUT
Rating
Terminal Voltage with
Respect to GND
Terminal Voltage with
Respect to GND
Operating Temperature
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current
Value
–0.5 to +4.6
–0.5 to V
DD
+0.5
0 to +70
–55 to +125
–55 to +125
1.2
50
Unit
V
V
o
o
o
Recommended Operating
Temperature and Supply Voltage
Grade
Commercial
Industrial
Temperature
0°C to +70°C
–40°C to +85°C
V
SS
0V
0V
V
DD
3.3V+10/-5%
3.3V+10/-5%
V
DDQ
3.3V+10/-5%
3.3V+10/-5%
3780 tbl 03
C
C
C
W
mA
3780 tbl 05
Recommended DC Operating
Conditions
Symbol
V
DD
V
DDQ
Parameter
Core Supply Voltage
I/O Supply Voltage
Min.
3.135
3.135
0
2.0
(1)
–0.5
(3)
Typ.
3.3
3.3
0
____
____
Max.
3.63
3.63
0
V
DDQ
+0.3
(2)
0.8
Unit
V
V
V
V
V
3780 tbl 04
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. V
DD
, V
DDQ
and input terminals only.
3. I/O terminals.
V
SS,
V
SSQ
Ground
V
IH
V
IL
Input High Voltage
Input Low Voltage
NOTES:
1. V
IH
and V
IL
as indicated is for both input and I/O pins.
2. V
IH
(max) = 6.0V for pulse width less than t
CYC
/2, once per cycle.
3. V
IL
(min) = –1.0V for pulse width less than t
CYC
/2, once per cycle.
Capacitance
Symbol
C
IN
C
I/O
(T
A
= +25°C, f = 1.0MHz, TQFP package)
Parameter
(1)
Input Capacitance
I/O Capacitance
Conditions
V
IN
= 3dV
V
OUT
= 3dV
Max.
4
8
Unit
pF
pF
3780 tbl 06
NOTE:
1. This parameter is guaranteed by device characterization, but not production
tested.
4
IDT71V633, 64K x 32, 3.3V Synchronous SRAM with
Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Pin Configuration
A
6
A
7
CE
CS
0
BW
4
BW
3
BW
2
BW
1
CS
1
V
DD
V
SS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
8
A
9
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
NC
I/O
16
I/O
17
V
DDQ
V
SSQ
I/O
18
I/O
19
I/O
20
I/O
21
V
SSQ
V
DDQ
I/O
22
I/O
23
V
SS
(1)
V
DD
NC
V
SS
I/O
24
I/O
25
V
DDQ
V
SSQ
I/O
26
I/O
27
I/O
28
I/O
29
V
SSQ
V
DDQ
I/O
30
I/O
31
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
PK100-1
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
I/O
15
I/O
14
V
DDQ
V
SSQ
I/O
13
I/O
12
I/O
11
I/O
10
V
SSQ
V
DDQ
I/O
9
I/O
8
V
SS
NC
V
DD
ZZ
(2)
I/O
7
I/O
6
V
DDQ
V
SSQ
I/O
5
I/O
4
I/O
3
I/O
2
V
SSQ
V
DDQ
I/O
1
I/O
0
NC
LBO
A
5
A
4
A
3
A
2
A
1
A
0
NC
NC
V
SS
V
DD
NC
NC
A
10
A
11
A
12
A
13
A
14
A
15
NC
3780 drw 02
.
Top View TQFP
NOTES
1. Pin 14 does not have to be directly connected to V
SS
as long as the input voltage is
≤
V
IL
.
2. Pin 64 can be left unconnected and the device will always remain in active mode.
5
6.42
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