Philips Semiconductors
Product specification
8-bit serial/parallel register with sign extend (3-State)
74F322
FEATURES
•
Multiplexed parallel I/O ports
•
Separate serial input and output
•
Sign extend function
•
3-State outputs for bus applications
•
Direct Overriding Clear
DESCRIPTION
The 74F322 is an 8-bit shift register with provision for either serial or
parallel loading and with 3-State parallel outputs plus a bi-state
serial output. Parallel data inputs and outputs are multiplexed to
minimize pin count. State changes are initiated by the rising edge of
the clock. Four synchronous modes of operation are possible: hold
(store), shift right with serial entry, shift right with sign extend, and
parallel load. An asynchronous Master Reset (MR) input overrides
clocked operation and clears the registers.
The 74F322 contains eight D-type edge triggered flip-flops and the
interstage gating required to perform right shift and the intrastage
gating necessary for hold and synchronous parallel load operations.
A Low signal on RE enables shifting or parallel loading, while a High
signal enables the hold mode. A High signal on S/P enables shift
right, while a Low signal disables the 3-State output buffers and
enables parallel loading. In the shift right mode a High signal on SE
enables serial entry from either D0 or D1, as determined by the S
input. A Low signal on SE enables shift right, but Q7 reloads its
contents, thus performing the sign extend function. A High signal on
OE disables the 3-State output buffers, regardless of the other
control inputs. In this condition the shifting and loading operations
can still be performed.
PIN CONFIGURATION
RE
S/P
D0
I/O0
I/O2
I/O4
I/O6
OE
MR
1
2
3
4
5
6
7
8
9
20 V
CC
19 S
18 SE
17 D1
16 I/O1
15 I/O3
14 I/O5
13 I/O7
12 Q7
11 CP
GND 10
SF00874
TYPE
74F322
TYPICAL f
MAX
125MHz
TYPICAL
SUPPLY CURRENT
(TOTAL)
60mA
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
20-pin plastic DIP
20-pin plastic SOL
COMMERCIAL RANGE
V
CC
= 5V
±10%,
T
amb
= 0°C to +70°C
N74F322N
N74F322D
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
D0, D1
S
SE
CP
S/P
RE
MR
OE
Q7
I/On
Serial data inputs
Serial data select input
Sign Extend input
Clock Pulse input (Active rising edge)
Serial (High) or Parallel (Low) mode control input
Register Enable input (Active Low)
Asynchronous Master Reset input (Active Low)
Output Enable input (Active Low)
Bi-state serial output
Multiplexed parallel data inputs or
DESCRIPTION
74F(U.L.)
HIGH/LOW
1.0/1.0
1.0/2.0
1.0/3.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
50/33
3.5/1.0
150/40
LOAD VALUE
HIGH/LOW
20µA/0.6mA
20µA/1.2mA
20µA/1.8mA
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
1.0mA/20mA
70µA/0.6mA
3.0mA/24mA
3-State parallel outputs
NOTE:
One (1.0) FAST Unit Load (U.L.) is defined as: 20µA in the High State and 0.6mA in the Low state.
1988 Apr 22
1
853-0366 93020
Philips Semiconductors
Product specification
8-bit serial/parallel register with sign extend (3-State)
74F322
LOGIC SYMBOL
3
17
LOGIC SYMBOL (IEEE/IEC)
9
8
1
2
11
18
19
3
SRG8
R
2EN15
G3
3M1[SHIFT]
3M2[PAR LOAD]
C6/1
→
G4
8, 4, 1, 6D
G5
8, 5, 1, 6D
8, 4, 1, 6D
2, 6D
7, 15
16
5
15
6
14
7
13
2, 6D
12, 13
Z14
12
2, 96D
8, 15
Z8
Z7
19
1
2
18
11
8
9
S
RE
S/P
SE
CP
OE
MR
I/O0
I/O1
D0
D1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
Q7
17
4
V
CC
= Pin 20
GND = Pin 10
4
16
5
15
6
14
7
13
12
SF00875
SF00876
FUNCTION TABLE
INPUTS
MR
L
L
H
H
H
H
H
X
X
*
H
L
NC
X
Z
↑
I0–I7
=
=
=
=
=
=
=
=
RE
H
X
L
L
L
L
H
S/P
X
H
L
H
H
H
X
SE
X
X
X
H
H
L
X
S
X
X
X
L
H
X
X
OE*
L
L
X
L
L
L
L
CP
X
X
↑
↑
↑
↑
X
I/O0
L
L
I0
D0
D1
O0
NC
I/O1
L
L
I1
O0
O0
O0
NC
I/O2
L
L
I2
O1
O1
O1
NC
I/O3
L
L
I3
O2
O2
O2
NC
INPUTS
I/O4
L
L
I4
O3
O3
O3
NC
I/O5
L
L
I5
O4
O4
O4
NC
I/O6
L
L
I6
O5
O5
O5
NC
I/O7
L
L
I7
O6
O6
O6
NC
Q7
L
L
I7
O6
O6
O6
NC
OPERATING
MODE
Clear
Parallel load
Shift right
Sign extend
Hold
D0–D7 =
O0–O7 =
↑
=
L
L
X
X
X
X
Z
Z
Z
Z
Z
Z
Z
Z
NC
3-State
X
X
X
X
H
↑
Z
Z
Z
Z
Z
Z
Z
Z
NC
When the input is High, all I/O terminals are at the high impedance state, sequential operation or clearing of the register is not
affected.
High voltage level
Low voltage level
No change
Don’t care
High impedance “off” state
Low-to-High clock transition
The level of the steady state input at the respective I/O terminal is loaded into the flip-flop while the flip-flop outputs (except Q7) are
isolated from the I/O terminal.
The level of the steady state inputs to the serial multiplexer input.
The level of the respective Qn flip-flop prior to the last clock Low-to-High transition.
Not a Low-to-High clock transition
1988 Apr 22
2
Philips Semiconductors
Product specification
8-bit serial/parallel register with sign extend (3-State)
74F322
LOGIC DIAGRAM
OE
RE
8
1
S/P
D1
S
D0
2
17
19
3
18
SE
CP
D
R
Q
Q
4
I/O0
CP
D
R
Q
Q
16
I/O1
CP
D
R
Q
Q
5
I/O2
CP
D
R
Q
Q
15
I/O3
CP
D
R
Q
Q
6
I/O4
CP
D
R
Q
Q
14
I/O5
CP
D
R
Q
Q
7
I/O6
12
Q7
CP
D
R
MR
V
CC
= Pin 20
GND = Pin 10
CP
9
11
Q
Q
13
I/O7
SF00877
1988 Apr 22
3
Philips Semiconductors
Product specification
8-bit serial/parallel register with sign extend (3-State)
74F322
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the
operating free-air temperature range.)
SYMBOL
V
CC
V
IN
I
IN
V
OUT
I
OUT
T
amb
T
stg
Supply voltage
Input voltage
Input current
Voltage applied to output in High output state
Current applied to output in Low output state
Operating free-air temperature range
Storage temperature
Q7
I/On
PARAMETER
RATING
–0.5 to +7.0
–0.5 to +7.0
–30 to +5
–0.5 to +5.5
40
48
0 to +70
–65 to +150
UNIT
V
V
mA
V
mA
mA
°C
°C
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
CC
V
IH
V
IL
I
IK
I
OH
Supply voltage
High-level input voltage
Low-level input voltage
Input clamp current
High-level output current
Q7
I/On
Low-level output current
Operating free-air temperature range
Q7
I/On
0
PARAMETER
MIN
4.5
2.0
0.8
–18
–1
–3
20
24
70
LIMITS
NOM
5.0
MAX
5.5
V
V
V
mA
mA
mA
mA
mA
°C
UNIT
I
OL
T
amb
1988 Apr 22
4
Philips Semiconductors
Product specification
8-bit serial/parallel register with sign extend (3-State)
74F322
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL
PARAMETER
TEST CONDITIONS
1
±10%V
CC
±5%V
CC
±10%V
CC
±5%V
CC
±10%V
CC
±5%V
CC
LIMITS
MIN
2.5
2.7
2.4
2.7
3.3
0.38
0.35
–0.73
0.55
0.50
–1.2
100
1
20
–1.8
V
CC
= MAX, V
I
= 0.5V
–1.2
–0.6
V
CC
= MAX, V
I
= 2.7V
V
CC
= MAX, V
I
= 0.5V
V
CC
= MAX
I
CCH
I
CC
Supply current (total)
I
CCL
I
CCZ
V
CC
= MAX
–60
50
60
65
70
–0.6
–150
75
90
95
3.4
TYP
2
MAX
UNIT
V
V
V
V
V
V
V
µA
mA
µA
mA
mA
mA
µA
mA
mA
mA
mA
mA
Q7
V
OH
High-level output voltage
I/On
V
CC
= MIN,
V
IL
= MAX,
V
IH
= MIN
V
CC
= MIN,
V
IL
= MAX,
V
IH
= MIN
I
OH
= –1mA
I
OH
= –3mA
V
OL
V
IK
I
I
I
IH
I
IL
Low-level output voltage
Input clamp voltage
Input current at
maximum input voltage
High-level input current
SE
Low-level input current
S
others
others
I/On
I
OL
= MAX
V
CC
= MIN, I
I
= I
IK
V
CC
= MAX, V
I
= 7.0V
V
CC
= MAX, V
I
= 5.5V
V
CC
= MAX, V
I
= 2.7V
I
IH +
I
OZH
I
IL +
I
OZL
I
OS
Off-state output current
High-level voltage applied
Off-state output current
Low-level voltage applied
Short-circuit output current
3
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V
CC
= 5V, T
amb
= 25°C.
3. Not more than one output should be shorted at a time. For testing I
OS
, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I
OS
tests should be performed last.
1988 Apr 22
5
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