INTEGRATED CIRCUITS
74F378
Hex D flip-flop with enable
Product specification
IC15 Data Handbook
1989 Oct 05
Philips
Semiconductors
Philips Semiconductors
Product specification
Hex D flip-flop with enable
74F378
FEATURES
•
6-bit high-speed parallel register
•
Positive edge-triggered D-type inputs
•
Fully buffered common Clock and Enable inputs
•
Input clamp diodes limit high speed termination effects
•
Fully TTL and CMOS compatible
DESCRIPTION
The 74F378 has six edge-triggered D-type flip-flops with individual
D inputs and Q outputs. The common buffered Clock (CP) input
loads all flip-flops simultaneously when the Enable (E) input is Low.
The register is fully edge-triggered. The state of each D input, one
setup time before the Low-to-High clock transition is transformed to
the corresponding flop-flop’s Q output. The E input must be stable
one setup time prior to the Low-to-High clock transition for
predictable operation.
TYPE
74F378
TYPICAL f
max
100MHz
TYPICAL SUPPLY
CURRENT (TOTAL)
35mA
ORDERING INFORMATION
DESCRIPTION
COMMERCIAL
RANGE
V
CC
= 5V
±
10%,
T
amb
= 0
°
C to +70
°
C
N74F378N
N74F378D
PKG DWG #
16–pin plastic DIP
16–pin plastic SO
SOT38-4
SOT109-1
PIN CONFIGURATION
E 1
Q0 2
D0 3
D1 4
Q1 5
D2 6
Q2 7
GND
8
16 V
CC
15 Q5
14 D5
13 D4
12 Q4
11 D3
10 Q3
9 CP
SF00927
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS
D0 – D5
CP
E
Data inputs
Clock pulse input (active rising edge)
Enable input (active low)
DESCRIPTION
74F (U.L.)
HIGH/LOW
1.0/1.0
1.0/1.0
1.0/1.0
50/33
LOAD VALUE
HIGH/LOW
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
1.0mA/20mA
Q0 – Q5
Data outputs
NOTE:
One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.
1989 Oct 05
2
853–0067 97804
Philips Semiconductors
Product specification
Hex D flip-flop with enable
74F378
LOGIC SYMBOL
3
4
6
11 13 14
IEC/IEEE SYMBOL
1
9
3
2D
4
6
Q0 Q1 Q2 Q3 Q4 Q5
11
13
2
5
7
10 12 15
14
15
10
12
G1
1C2
2
5
7
D0 D1 D2 D3 D4 D5
9
1
CP
E
V
CC
= Pin 16
GND = Pin 8
SF00916
SF00917
LOGIC DIAGRAM
D0
3
E
1
D1
4
D2
6
D3
11
D4
13
D5
14
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
CP
9
2
Q0
Q1
5
Q2
7
Q3
10
Q4
12
Q5
15
V
CC
= Pin 16
GND = Pin 8
SF00918
FUNCTION TABLE
INPUTS
E
l
l
h
H
H =
h =
L =
l =
X =
↑
=
CP
↑
↑
Dn
h
l
OUTPUTS
Qn
H
L
OPERATING
MODE
Load “1”
Load “0”
Hold (do nothing)
↑
X
no change
X
X
no change
High-voltage level
High-voltage level one setup time
prior to the Low-to-High clock transition
Low-voltage level
Low-voltage level one setup time
prior to the Low-to-High clock transition
Don’t care
Low-to-High clock transition
1989 Oct 05
3
Philips Semiconductors
Product specification
Hex D flip-flop with enable
74F378
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the
operating free-air temperature range.)
SYMBOL
V
CC
V
IN
I
IN
V
OUT
I
OUT
T
amb
T
stg
Supply voltage
Input voltage
Input current
Voltage applied to output in High output state
Current applied to output in Low output state
Operating free-air temperature range
Storage temperature range
PARAMETER
RATING
–0.5 to +7.0
–0.5 to +7.0
–30 to +5
–0.5 to V
CC
40
0 to +70
–65 to +150
UNIT
V
V
mA
V
mA
°
C
°
C
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
V
CC
V
IH
V
IL
I
IK
I
OH
I
OL
T
amb
Supply voltage
High-level input voltage
Low-level input voltage
Input clamp current
High-level output current
Low-level output current
Operating free-air temperature range
0
PARMETER
SYMBOL
MIN
4.5
2.0
0.8
–18
–1
20
70
NOM
5.0
MAX
5.5
UNIT
V
V
V
mA
mA
mA
°
C
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL
PARAMETER
TEST
CONDITIONS
1
V
CC
= MIN, V
IL
= MAX,
V
OH
High-level
High level output voltage
V
IH
= MIN, I
OH
= MAX
Low-level
Low level output voltage
Input clamp voltage
Input current at maximum input voltage
High-level input current
Low-level input current
Short-circuit output current
3
Supply current (total)
I
CCH
I
CCL
V
CC
= MIN, V
IL
= MAX,
V
IH
= MIN, I
OL
= MAX
V
CC
= MIN, I
I
= I
IK
V
CC
= MAX, V
I
= 7.0V
V
CC
= MAX, V
I
= 2.7V
V
CC
= MAX, V
I
= 0.5V
V
CC
= MAX
V
CC
= MAX
–60
32
35
±10%V
CC
±5%V
CC
±10%V
CC
±5%V
CC
MIN
2.5
2.7
3.4
0.30
0.30
–0.73
0.50
0.50
–1.2
100
20
–0.6
–150
45
45
LIMITS
TYP
2
MAX
V
V
V
V
V
µA
µA
mA
mA
mA
mA
UNIT
V
O
OL
V
IK
I
I
I
IH
I
IL
I
OS
I
CC
Notes:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V
CC
= 5V, T
amb
= 25
°
C.
3. Not more than one output should be shorted at a time. For testing I
OS
, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I
OS
tests should be performed last.
1989 Oct 05
4
Philips Semiconductors
Product specification
Hex D flip-flop with enable
74F378
AC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST
CONDITION
Waveform 1
Waveform 1
T
amb
= +25°C
V
CC
= +5.0V
C
L
= 50pF, R
L
= 500Ω
MIN
f
MAX
t
PLH
t
PHL
Maximum clock frequency
Propagation delay
CP to Qn
80
3.0
3.5
TYP
100
5.5
6.0
7.5
8.5
MAX
T
amb
= 0°C to +70°C
V
CC
= +5.0V
±
10%
C
L
= 50pF, R
L
= 500Ω
MIN
80
3.0
3.5
8.5
9.5
MAX
MHz
ns
UNIT
AC SETUP REQUIREMENTS
LIMITS
SYMBOL
PARAMETER
TEST
CONDITION
T
amb
= +25°C
V
CC
= +5.0V
C
L
= 50pF, R
L
= 500Ω
MIN
t
s
(H)
t
s
(L)
t
h
(H
)
t
h
(L)
t
s
(H)
t
s
(L)
t
h
(H
)
t
h
(L)
t
w
(H)
t
w
(L)
Setup time, High or Low
Dn to CP
Hold time, High or Low
Dn to CP
Setup time, High or Low
E to CP
Hold time, High or Low
E to CP
CP Pulse width,
High or Low
Waveform 2
Waveform 2
Waveform 2
Waveform 2
Waveform 1
4.0
4.0
0
0
4.0
10.0
0
0
4.0
6.0
TYP
MAX
T
amb
= 0°C to +70°C
V
CC
= +5.0V
±
10%
C
L
= 50pF, R
L
= 500Ω
MIN
4.0
4.0
0
0
4.0
10.0
0
0
4.0
6.0
MAX
ns
ns
ns
ns
ns
UNIT
AC WAVEFORMS
For all waveforms, V
M
= 1.5V.
The shaded areas indicate when the input is permitted to change for predictable output performance.
1/f
MAX
CP
Dn
V
M
t
w
(H)
t
PHL
V
M
t
w
(L)
t
PLH
En
Qn
V
M
t
s
(L)
t
h
=0
V
M
t
s
(H)
t
h
=0
V
M
V
M
V
M
V
M
V
M
V
M
V
M
V
M
t
s
V
M
t
h
SF00919
CP
Waveform 1. Propagation Delay, Clock Input to Output,
Clock Pulse Width, and Maximum Clock Frequency
SF00920
Waveform 2. Data and Enable Setup Time and Hold Times
1989 Oct 05
5
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