8-bit shift register with input storage registers (3-State)
74F598
FEATURES
•
High impedance PNP base input for reduced loading (20µA in
High and Low states)
•
8–bit parallel storage register
•
Shift register has asynchronous direct overriding reset
•
Shift load SHLD is functional when SHCP is Low and locked out
when SHCP is High.
•
Guaranteed shift frequency DC to 105MHz
•
Parallel 3–State I/O storage register inputs and shift register
parallel outputs
The shift register load function has been modified to load when both
SHLD and SHCP are Low. When SHCP is High the shift register
load operation is not performed. Data will be properly shifted on the
rising edge of SHCP when SHLD is High.
TYPE
74F598
TYPICAL SHCP f
max
100MHz
TYPICAL SUPPLY
CURRENT (TOTAL)
75mA
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
COMMERCIAL RANGE
V
CC
= 5V
±
10%,
T
amb
= 0
°
C to +70
°
C
N74F598N
N74F598D
PKG DWG #
DESCRIPTION
The 74F598 consists of an 8–bit storage register feeding a
parallel–in/serial–in, parallel–out/serial–out 8–bit shift register. Both
the storage register and shift register have positive edge–triggered
clocks. The shift register has asynchronous reset and when SHCP
is Low, it has asynchronous load.
20–pin plastic DIP
20–pin plastic SOL
SOT146-1
SOT163-1
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS
I/On
Ds0, Ds1
SHCP
STCP
SHCPEN
SHLD
SHRST
S
OE
Qs
Parallel data input
Serial data inputs
Shift register clock pulse input
Storage register clock pulse input
Shift register clock pulse enable input
Shift register load input (active Low)
Shift register reset input (active Low)
Serial data select input
Output enable input
Serial data output
DESCRIPTION
74F (U.L.) High/
Low
1.0/0.033
1.0/0.033
1.0/0.033
1.0/0.033
1.0/0.033
1.0/0.033
1.0/0.033
1.0/0.033
1.0/0.033
50/33
150/40
LOAD VALUE
High/Low
20µA/20µA
20µA/20µA
20µA/20µA
20µA/20µA
20µA/20µA
20µA/20µA
20µA/20µA
20µA/20µA
20µA/20µA
1.0mA/20mA
3.0mA/24mA
I/On
Parallel data outputs
Note to input and output loading and fan out table
1. One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.
PIN CONFIGURATION
I/O0 1
I/O1 2
I/O2 3
I/O3 4
I/O4 5
I/O5 6
I/O6 7
I/O7 8
SHLD 9
GND 10
20 V
CC
19 S
18 DS0
LOGIC SYMBOL
18
17
1
2
3
4
5
6
7
8
Ds0 Ds1 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7
19
S
OE
STCP
SHCPEN
SHCP
SHRST
SHLD
Qs
17 DS1
16 OE
15 STCP
14 SHCPEN
13 SHCP
12 SHRST
11 Qs
16
15
14
13
12
9
SF00375
V
CC
= Pin 20
GND = Pin 10
11
SF00376
1991 Oct 21
2
853–1583 04407
Philips Semiconductors
Product specification
8-bit shift register with input storage registers (3-State)
74F598
IEC/IEEE SYMBOL
16
12
14
13
9
15
19
18
17
1
C1
G1
1, 5D
1, 5D
2D
6, 14
2
2D
7, 14
3
4
5
6
7
8
2D
13, 14
3D
Z13
11
Z6
3D
C2
SRG8
EN14
R
G4
4C5/4→
3D
Z7
SF00377
FUNCTION TABLE
INPUTS
SHRST
L
L
X
H
H
H
H
X
H
H
STCP
X
X
↑
X
X
↑
↑
X
↑
↑
SHCP
L
L
X
↑
↑
L
L
X
X
H
SHLD
H
L
X
H
H
L
L
X
H
X
S
X
X
X
L
H
X
X
X
X
X
OE*
L
L
H
L
L
H
X
H
X
X
I0
Ds0
Ds1
I0
O0
Z
NC
NC
I1
O0
O0
I1
O1
Z
NC
NC
I2
O1
O1
I2
O2
Z
NC
NC
I3
O2
O2
I3
O3
Z
NC
NC
I4
O3
O3
I4
O4
Z
NC
NC
I5
O4
O4
I5
O5
Z
NC
NC
I6
O5
O5
I6
O6
Z
NC
NC
I7
O6
O6
I7
O7
Z
NC
NC
O7
O6
O6
O7
O7
NC
NC
NC
Load data directly to shift regis-
ter
Data transferred from storage
register to shift register
3–State
Hold
Hold (no storage or shift register
load
I/O0
L
I/O1
L
I/O2
L
INPUTS/OUTPUTS
I/O3
L
I/O4
L
I/O5
L
I/O6
L
I/O7
L
Q7
L
Clear shift register
Invalid, state of shift register in-
determinate when signal is re-
moved
Load data to storage register
Shift right
OPERATING MODE
Notes to function table
D0 – D7 = The level of the steady state inputs to the serial multiplexer.
H = High voltage level
I0 – I7 = The level of the steady state input at the respective I/O terminal is loaded into the flip–flop while the flip–flop outputs ( except Q7) are isolated
from the I/O terminal.
L = Low voltage level
NC= No change
O0 – O7 = The level of the respective Qn flip–flop prior to the last clock Low–to–High transition
X = Don’t care
Z = High impedance ”off” state
* = When the OE input is High, all I/O terminals are at the High impedance state, sequential operation or cleaning of the register is not affected.
↑
= Low–to–High clock transition
↑
= Not Low–to–High clock transition
1991 Oct 21
3
Philips Semiconductors
Product specification
8-bit shift register with input storage registers (3-State)
74F598
LOGIC DIAGRAM
16
OE 12
SHRST
14
13
9
19
18
17
15
1
1D
S
C1
2
R
C2 3S
S
C1
3
R
C2 3S
S
C1
4
R
C2 3S
S
C1
5
R
C2 3S
S
C1
6
1D
S
C1
7
1D
S
C1
8
1D
S
C1
V
CC
= Pin 20
GND = Pin 10
R
R
C2 3S
3R
9
Qs
R
C2 3S
3R
R
C2 3S
3R
3R
3R
3R
3R
C2
2D
SHCPEN
SHCP
SHLD
S
Ds0
Ds1
STCP
I/O0
I/O1
1D
I/O2
1D
I/O3
1D
I/O4
1D
I/O5
I/O6
I/O7
SF00378
1991 Oct 21
4
Philips Semiconductors
Product specification
8-bit shift register with input storage registers (3-State)
74F598
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the
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