Philips Semiconductors
Product specification
Transceivers/registers
74F651A Octal transceiver/register, inverting (3-State)
74F652A Octal transceiver/register, non-inverting (3-State)
FEATURES
74F651A/74F652A
•
Combines 74F245 and two 74F374 type functions in one chip
•
High impedance base inputs for reduced loading (70µA in high
and low states)
DESCRIPTION
The 74F651A and 74F652A transceivers/registers consist of bus
transceiver circuits with 3–State outputs, D–type flip–flops, and
control circuitry arranged for multiplexed transmission of data
directly from the input bus or the internal registers. Data on the A or
B bus will be clocked into the registers as the appropriate clock pin
goes high. Output enable (OEAB, OEBA) and select (SAB, SBA)
pins are provided for bus management.
•
Independent registers for A and B buses
•
Multiplexed real-time and stored data
•
Choice of non-inverting and inverting data paths
•
3-State outputs
•
Industrial temperature range available (–40°C to +85°C) for
74F652A
TYPE
74F651/74F652
74F651A/74F652A
TYPICAL f
max
110MHz
175MHz
TYPICAL SUPPLY CURRENT( TOTAL)
140mA
110mA
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
COMMERCIAL RANGE
V
CC
= 5V
±10%,
T
amb
= 0°C to +70°C
N74F651AN, N74F652AN
N74F651AD, N74F652AD
INDUSTRIAL RANGE
V
CC
= 5V
±10%,
T
amb
= –40°C to +85°C
I74F652AN
I74F652AD
PKG DWG #
24–pin plastic slim DIP (300mil)
24–pin plastic SOL
SOT222-1
SOT137-1
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS
A0 – A7, B0 – B7
CPAB, CPBA
SAB, SBA
OEAB, OEBA
A0 – A7, B0 – B7
A0 – A7, B0 – B7
A0 – A7, B0 – B7
A, B inputs
A–to–B, B–to–A clock inputs
A–to–B, B–to–A select inputs
A–to–B, B–to–A output enable inputs
A, B outputs for N74F651, N74F652
A, B outputs for N74F651A, N74F652A
A, B outputs for I74F652A
DESCRIPTION
74F (U.L.) HIGH/LOW
3.5/0.116
1.0/0.033
1.0/0.033
1.0/0.033
750/106.7
750/80
750/60
LOAD VALUE HIGH/LOW
70µA/70µA
20µA/20µA
20µA/20µA
20µA/20µA
15mA/64mA
15mA/48mA
15mA/36mA
Note to input and output loading and fan out table
1. One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state.
1999 Jun 23
2
853–1126 21852
Philips Semiconductors
Product specification
Transceivers/registers
74F651A/74F652A
The following examples demonstrate the four fundamental
bus-management functions that can be performed with the 74F651A
and 74F652A. The select pins determine whether data is stored or
transferred through the device in real time. The output enable pins
determine the direction of the data flow.
BUS MANAGEMENT FUNCTIONS
REAL TIME BUS TRANSFER
BUS B TO BUS A
REAL TIME BUS TRANSFER
BUS A TO BUS B
STORAGE FROM
A, B, OR A AND B
TRANSFER STORED DATA
TO A AND/OR B
BUS A
BUS B
BUS A
BUS B
BUS A
BUS B
BUS A
BUS B
OEAB OEBA CPAB CPBA SAB SBA
L
L
X
X
X
L
OEAB OEBA CPAB CPBA SAB SBA
H
H
X
X
L
X
OEAB OEBA CPAB CPBA SAB SBA
X
L
L
H
X
H
↑
X
↑
X
↑
↑
X
X
X
X
X
X
OEAB OEBA CPAB CPBA SAB SBA
H
L
H or L H or L H
H
SF00409
FUNCTION TABLE
INPUTS
OEAB
L
L
X
H
L
L
L
L
H
H
H
H
OEBA
H
H
H
H
X
L
L
L
H
H
L
L
CPAB
H or L
↑
↑
↑
H or L
↑
X
X
X
H or L
H or L
H or L
CPBA
H or L
↑
H or L
↑
↑
↑
X
H or L
X
X
H or L
H or L
SAB
X
X
X
L
X
X
X
X
L
H
H
H
SBA
X
X
X
X
X
L
L
H
X
X
H
H
An
Input
Input
Input
Input
Unspecified*
Output
Output
Output
Input
Input
Output
Output
DATA I/O
Bn
Input
Input
Unspecified*
Output
Input
Input
Input
Input
Output
Output
Output
Output
OPERATING MODE
74F651A
Isolation
Store A and B data
Store A, hold B
Store A in both registers
Hold A, store B
Store B in both registers
Real time B data to A bus
Stored B data to A bus
Real time A data to B bus
Stored A data to B bus
Stored A data to B bus
Stored B data to A bus
74F652A
Isolation
Store A and B data
Store A hold B
Store A in both registers
Hold A, store B
Store B in both registers
Real time B data to A bus
Stored B data to A bus
Real time A data to B bus
Stored A data to B bus
Stored A data to B bus
Stored B data to A bus
Notes to function table
1. H = High-voltage level
2. L = Low-voltage level
3. * = The data output function may be enabled or disabled by various signals at the OEBA and OEAB inputs. Data input functions are
always enabled, i.e., data at the bus pins will be stored on every low-to-high transition of the clock.
4.
↑
= Low-to-high clock transition
5. X = Don’t care
1999 Jun 23
5
微控制器 MCU
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