INTEGRATED CIRCUITS
74F85
4-bit magnitude comparator
Product specification
IC15 Data Handbook
1994 Sep 27
Philips Semiconductors
Philips Semiconductors
Product specification
4-bit magnitude comparator
74F85
FEATURES
•
High-impedance NPN base inputs for reduced loading
(20µA in High and Low states)
PIN CONFIGURATION
B3
I
A<B
I
A=B
I
A>B
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
A3
B2
A2
A1
B1
A0
B0
•
Magnitude comparison of any binary words
•
Serial or parallel expansion without extra gating
DESCRIPTION
The 74F85 is a 4-bit magnitude comparator that can be expanded to
almost any length. It compares two 4-bit binary, BCD, or other
monotonic codes and presents the three possible magnitude results
at the outputs. The 4-bit inputs are weighted (A0–A3) and (B0–B3)
where A3 and B3 are the most significant bits. The operation of the
74F85 is described in the Function Table, showing all possible logic
conditions. The upper part of the table describes the normal
operation under all conditions that will occur in a single device or in
a series expansion scheme. In the upper part of the table the three
outputs are mutually exclusive. In the lower part of the table, the
outputs reflect the feed-forward conditions that exist in the parallel
expansion scheme. The expansion inputs I
A>B
, and I
A=B
and I
A<B
are the least significant bit positions. When used for series
expansion, the A>B, A=B and A<B outputs of the lease significant
word are connected to the corresponding I
A>B
, I
A=B
and I
A<B
inputs
of the next higher stage. Stages can be added in this manner to any
length, but a propagation delay penalty of about 15ns is added with
each additional stage. For proper operation, the expansion inputs of
the least significant word should be tied as follows: I
A>B
= Low,
I
A=B
= High, and I
A<B
= Low.
A>B
A=B
A<B
GND
SF00075
TYPE
TYPICAL
PROPAGATION
DELAY
7.0ns
TYPICAL
SUPPLY CURRENT
(TOTAL)
40mA
74F85
ORDERING INFORMATION
DESCRIPTION
16-pin plastic DIP
16-pin plastic SO
COMMERCIAL RANGE
V
CC
= 5V
±10%,
T
amb
= 0°C to +70°C
N74F85N
N74F85D
PKG DWG #
SOT38-4
SOT162-1
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS
A0–A3
B0–B3
I
A<B
, I
A=B
, I
A>B
A<B, A=B, A>B
DESCRIPTION
Comparing inputs
Comparing inputs
Expansion inputs (active High)
Data outputs (active High)
74F (U.L.) HIGH/LOW
1.0/0.033
1.0/0.033
1.0/0.033
50/33
LOAD VALUE HIGH/LOW
20µA/20µA
20µA/20µA
20µA/20µA
1.0mA/20mA
NOTE:
One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.
LOGIC SYMBOL
10
12
13
15
9
11
14
1
IEC/IEEE SYMBOL
10
12
13
P
3
0
Q
3
<
=
>
P<Q
P=Q
P>Q
7
6
5
0
COMP
A0
2
3
4
I
A<B
I
A=B
I
A>B
A1
A2
A3
B0
B1
B2
B3
15
9
11
14
1
A>B
A=B
A<B
2
3
V
CC
= Pin 16
GND = Pin 8
4
5
6
7
SF00076
SF00077
September 27, 1994
2
853–0055 13903
Philips Semiconductors
Product specification
4-bit magnitude comparator
74F85
LOGIC DIAGRAM
A3
B3
15
1
5
A>B
A2
B2
I
A<B
I
A=B
I
A>B
13
14
2
3
4
12
11
6
A=B
A1
B1
7
A<B
A0
B0
10
9
V
CC
= Pin 16
GND = Pin 8
SF00078
FUNCTION TABLE
COMPARING INPUTS
A3,B3
A3>B3
A3<B3
A3=B3
A3=B3
A3=B3
A3=B3
A3=B3
A3=B3
A3=B3
A3=B3
A3=B3
A3=B3
A3=B3
A2,B2
X
X
A2>B2
A2<B2
A2=B2
A2=B2
A2=B2
A2=B2
A2=B2
A2=B2
A2=B2
A2=B2
A2=B2
A1,B1
X
X
X
X
A1>B1
A1<B1
A1=B1
A1=B1
A1=B1
A1=B1
A1=B1
A1=B1
A1=B1
A1=B1
A0,B0
X
X
X
X
X
X
A0>B0
A0<B0
A0=B0
A0=B0
A0=B0
A0=B0
A0=B0
A0=B0
I
A>B
X
X
X
X
X
X
X
X
H
L
L
X
H
L
EXPANSION INPUTS
I
A<B
X
X
X
X
X
X
X
X
L
H
L
X
H
L
I
A=B
X
X
X
X
X
X
X
X
L
L
H
H
L
L
A>B
H
L
H
L
H
L
H
L
H
L
L
L
L
H
OUTPUTS
A<B
L
H
L
H
L
H
L
H
L
H
L
L
L
H
A=B
L
L
L
L
L
L
L
L
L
L
H
H
L
L
A3=B3
A2=B2
H = High voltage level
L = Low voltage level
X = Don’t care
September 27, 1994
3
Philips Semiconductors
Product specification
4-bit magnitude comparator
74F85
APPLICATION
INPUTS
(LSB)
B23
A23
B22
A22
B21
A21
B20
A20
B19
L
A19
B18
A18
B17
A17
B16
A16
B15
A15
B14
L
A14
B13
A13
B12
A12
B11
A11
B10
A10
B9
L
A9
B8
A8
B7
A7
B6
A6
B5
A5
B4
L
A4
B3
A3
B2
A2
B1
A1
(LSB)
B0
A0
L
H
L
B3
A3
B2
A2
B1
A1
B0
A0
I
A<B
I
A=B
I
A>B
B3
A3
B2
A2
B1
A1
B0
A0
I
A<B
I
A=B
I
A>B
B3
A3
B2
A2
B1
A1
B0
A0
I
A<B
I
A=B
I
A>B
B3
A3
B2
A2
B1
A1
B0
A0
I
A<B
I
A=B
I
A>B
B3
A3
B2
A2
B1
A1
B0
A0
I
A<B
I
A=B
I
A>B
A<B
A=B
A>B
A<B
A=B
A>B
NC
A<B
A=B
A>B
NC
B3
A3
B2
A2
B1
A1
B0
A0
A<B
A=B
A>B
A<B
A=B
A>B
OUTPUTS
A<B
A=B
A>B
NC
A<B
A=B
A>B
NC
The parallel expansion scheme shown in Figure 1 demonstrates the
most efficient general use of these comparators. The expansion
inputs can be used as a fifth input bit position except on the least
significant device, which must be connected as in the serial scheme.
The expansion inputs used by labeling I
A>B
as an “A” input, I
A<B
as
a “B” input and setting I
A=B
= Low. The 74F85 can be used as a 5-bit
comparator only when the outputs are used to drive the (A0–A3) and
(B0–B3) inputs of another 74F85 device. The parallel technique can
be expanded to any number of bits as shown in Table 1.
Table 1.
WORD LENGTH
1–4 bits
5–24 bits
25–120 bits
NUMBER OF
PACKAGES
1
2–6
8–31
TYPICAL SPEEDS
74F
12ns
22ns
34ns
SF00079
Figure 1. Comparison of Two 24-Bit Words
September 27, 1994
4
Philips Semiconductors
Product specification
4-bit magnitude comparator
74F85
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limits set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free-air temperature range.)
SYMBOL
V
CC
V
IN
I
IN
V
OUT
I
OUT
T
amb
T
stg
Supply voltage
Input voltage
Input current
Voltage applied to output in High output state
Current applied to output in Low output state
Operating free-air temperature range
Storage temperature range
PARAMETER
RATING
–0.5 to +7.0
–0.5 to +7.0
–30 to +5
–0.5 to V
CC
40
0 to +70
–65 to +150
UNIT
V
V
mA
V
mA
°C
°C
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
V
CC
V
IH
V
IL
I
IK
I
OH
I
OL
T
amb
Supply voltage
High-level input voltage
Low-level input voltage
Input clamp current
High-level output current
Low-level output current
Operating free-air temperature range
0
PARAMETER
MIN
4.5
2.0
0.8
–18
–1
20
+70
NOM
5.0
MAX
5.5
V
V
V
mA
mA
mA
°C
UNIT
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL
PARAMETER
TEST CONDITIONS
1
V
CC
= MIN, V
IL
= MAX
V
IH
= MIN, I
OH
= MAX
Low-level
Low level output voltage
Input clamp voltage
Input current at maximum input voltage
High-level input current
Low-level input current
Short-circuit output current
3
I
CCH
I
CC
Supply current (total)
I
CCL
V
CC
= MAX
V
CC
= MIN, V
IL
= MAX
V
IH
= MIN, I
OL
= MAX
V
CC
= MIN, I
I
= I
IK
V
CC
= 0.0V, V
I
= 7.0V
V
CC
= MAX, V
I
= 2.7V
V
CC
= MAX, V
I
= 0.5V
V
CC
= MAX
V
IN
= GND
An = Bn = I
A=B
= GND,
I
A>B
= I
A<B
= 4.5V
–60
36
40
±10%V
CC
±5%V
CC
±10%V
CC
±5%V
CC
LIMITS
MIN
2.5
2.7
3.4
0.30
0.30
–0.73
0.50
0.50
–1.2
100
20
–20
–150
50
54
mA
V
µA
µA
µA
mA
V
TYP
2
MAX
UNIT
V
O
OH
High level output voltage
High-level
V
V
O
OL
V
IK
I
I
I
IH
I
IL
I
OS
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V
CC
= 5V, T
amb
= 25°C.
3. Not more than one output should be shorted at a time. For testing I
OS
, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I
OS
tests should be performed last.
September 27, 1994
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
