NAND01G-N
1 Gbit (x8/x16) 2112 Byte Page NAND Flash Memory and
512 Mbit (x16) LPSDRAM, 1.8V, Multi-Chip Package
PRELIMINARY DATA
Features summary
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Multi-chip Package
– NAND Flash Memory
– 512 Mbit or 1 Gbit (x8/x16) Large Page
Size NAND Flash Memory
– 512 Mbit (x16) SDR or DDR LPSDRAM
Temperature range
– -30 up to 85 °C
Supply voltage
– NAND Flash : V
DDF
= 1.7V to 1.95V
– LPSDRAM: V
DDD
= V
DDQD
= 1.7V to 1.9V
Electronic Signature
ECOPACK
packages
FBGA
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TFBGA107 10.5 x 13 x 1.2mm
TFBGA149 10 x 13.5 x 1.2mm
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SDR/DDR LPSDRAM
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Flash Memory
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Interface: x16 bus width
Programmable Partial Array Self Refresh
Auto Temperature Compensated Self Refresh
Deep Power Down mode
1.8V LVCMOS interface
Quad internal Banks controlled by BA0 and
BA1
Wrap sequence: Sequential/Interleaved
Automatic and Controlled Precharge
Auto Refresh and Self Refresh
8,192 Refresh Cycles/64ms
Burst Termination by Burst Stop command and
Precharge Command
Nand Interface
– x8 or x16 bus width
– Multiplexed address/data
Page size
– x8 device: (2048 + 64 spare) Bytes
– x16 device: (1024 + 32 spare) Words
Block size
– x8 device: (128K + 4K spare) Bytes
– x16 device: (64K + 2K spare) Words
Page Read/Program
– Random access: 25µs (max)
– Sequential access: 50ns (min)
– Page program time: 300µs (typ)
Copy Back Program mode
– Fast page copy without external buffering
Fast Block Erase
– Block Erase time: 2ms (typ)
Chip Enable ‘don’t care’
– for simple interfacing with microcontrollers
Status Register
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January 2006
Rev1.0
1/23
www.st.com
2
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
NAND01G-N
Table 1.
Reference
NAND01G-N
NAND01GR4N5
1Gbit 1.8V (x16) DDR 512Mbit (x16) 1.8V, 133 MHz
TFBGA149
1. SDR = Single Data Rate; DDR = Double Data Rate.
Product List
Part Number
NAND01GR3N6
NAND Product
1Gbit 1.8V (x8)
LPSDRAM Product
(1)
SDR 512Mbit (x16) 1.8V, 133MHz
Package
TFBGA107
2/23
Rev1.0
NAND01G-N
Contents
Contents
1
Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
NAND Flash component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
LPSDRAM component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2
Signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
2.12
2.13
2.14
2.15
2.16
2.17
2.18
2.19
2.20
2.21
2.22
2.23
2.24
2.25
2.26
Flash memory Inputs/Outputs (I/O0-I/O7) . . . . . . . . . . . . . . . . . . . . . . . . 12
Flash memory Inputs/Outputs (I/O8-I/O15) . . . . . . . . . . . . . . . . . . . . . . . 12
Flash memory Address Latch Enable (AL) . . . . . . . . . . . . . . . . . . . . . . . 12
Flash memory Command Latch Enable (CL) . . . . . . . . . . . . . . . . . . . . . . 12
Flash memory Chip Enable (EF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Flash memory Read Enable (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Flash memory Write Enable (WF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Flash memory Write Protect (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Flash memory Ready/Busy (RB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Flash memory V
DDF
supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Flash memory V
SSF
ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
LPSDRAM Address Inputs (A0-A12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
LPSDRAM Bank Select Address Inputs (BA0-BA1) . . . . . . . . . . . . . . . . . 14
LPSDRAM Data Inputs/Outputs (DQ0-DQ15) . . . . . . . . . . . . . . . . . . . . . 14
LPSDRAM Chip Select (ED) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
LPSDRAM Column Address Strobe (CAS) . . . . . . . . . . . . . . . . . . . . . . . 14
LPSDRAM Row Address Strobe (RAS) . . . . . . . . . . . . . . . . . . . . . . . . . . 14
LPSDRAM Write Enable (WD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
LPSDRAM Clock Input (K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
LPSDRAM Clock Input (K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
LPSDRAM Clock Enable (KE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
LPSDRAM Lower/Upper Data Input/Output Mask (DQM0, DQM1) . . . . . 15
Lower/Upper Data Read/Write Strobe Input/Output (LDQS, UDQS) . . . . 15
LPSDRAM V
DDD
supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
LPSDRAM V
DDQD
supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
LPSDRAM V
SSD
ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Rev1.0
3/23
Contents
NAND01G-N
3
4
5
6
7
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4/23
Rev1.0
NAND01G-N
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Product List. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
TFBGA107 10.5x13mm - 10x14 active ball array, 0.80mm pitch, mechanical data . . . . . . 19
TFBGA149 10x13.5mm - 12x16 active ball array, 0.80mm pitch, mechanical data . . . . . . 20
Ordering Information Scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Rev1.0
5/23
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