MT9D131
1/3.2-Inch
System‐On‐A‐Chip (SOC)
CMOS Digital Image Sensor
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General Description
The ON Semiconductor MT9D131 is a 1/3.2 inch, 2 Mp CMOS
image sensor with an integrated advanced camera system. The camera
system features a microcontroller (MCU) and a sophisticated image
flow processor (IFP) with a real-time JPEG encoder.
The microcontroller manages all components of the camera system
and sets key operation parameters for the sensor core to optimize the
quality of raw image data entering the IFP. The sensor core consists of
an active pixel array of 1668 x 1248 pixels, programmable timing and
control circuitry including a PLL, analog signal chain with automatic
offset correction and programmable gain, and two 10-bit A/D
converters (ADC). The entire system-on-a-chip (SOC) has ultra-low
power requirements and superior low-light performance that is
particularly suitable for surveillance applications.
The excellent low-light performance of MT9D131 is one of the
hallmarks of ON Semiconductor’s breakthrough low-noise CMOS
imaging technology that achieves CCD image quality (based on
signal-to-noise ratio and low-light sensitivity) while maintaining the
inherent size, cost, power consumption, and integration advantages of
CMOS.
Feature Overview
48 CLCC
CASE TBD
ORDERING INFORMATION
See detailed ordering and shipping information on page 4 of
this data sheet.
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High Resolution Security Camera
•
Wireless Cameras
•
Consumer Video Products
Features
The MT9D131 is a color image sensor with a Bayer color filter
arrangement. Its basic characteristics are described in Table 1.
The MT9D131 has an embedded phase-locked loop oscillator (PLL)
that can be used with the common wireless system clock. When in use,
the PLL adjusts the incoming clock frequency, allowing the MT9D131
to run at almost any desired resolution and frame rate. To reduce
power consumption, the PLL can be bypassed and powered down.
Low power consumption is a very important requirement for all
components of wireless devices. The MT9D131 has numerous power
conserving features, including an ultra low-power standby mode and
the ability to individually shut down unused digital blocks.
Another important consideration for wireless devices is their
electromagnetic emission or interference (EMI). The MT9D131 has a
programmable I/O slew rate to minimize its EMI and an output FIFO
to eliminate output data bursts.
The advanced IFP and flexible programmability of the MT9D131
provide a variety of ways to enhance and optimize the image sensor
performance. Built-in optimization algorithms enable the MT9D131
to operate at factory settings as a fully automatic, highly adaptable
camera. However, most of its settings are user-programmable.
Applications
•
Superior Low-light Performance
•
Ultra-low-power, Cost Effective
•
Internal Master Clock Generated by on-chip
•
•
•
•
•
•
•
•
Phase- locked Loop Oscillator (PLL)
Electronic Rolling Shutter (ERS),
Progressive Scan
Integrated Image Flow Processor (IFP) for
Single-die Camera Module
Automatic Image Correction and
Enhancement, Including Lens Shading
Correction
Arbitrary Image Decimation with
Anti-aliasing
Integrated Real-time JPEG Encoder
Integrated Microcontroller for Flexibility
Two-wire Serial Interface Providing Access
to Registers and Microcontroller Memory
Selectable Output Data Format: ITU-R
BT.601 (YCbCr), 565RGB, 555RGB,
444RGB, JPEG 4:2:2, JPEG 4:2:0, and raw
10-bit
Output FIFO for Data Rate Equalization
Programmable I/O Slew Rate
•
Network Security Cameras
•
ePTZ Cameras
•
•
©
Semiconductor Components Industries, LLC, 2006
November, 2016
−
Rev. 9
1
Publication Order Number:
MT9D131/D
MT9D131
TABLE OF CONTENTS
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Typical Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Architecture Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Registers and Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
IFP Registers, Page 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
JPEG Indirect Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Output Format and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Sensor Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Feature Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Firmware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Start-Up and Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Spectral Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Appendix A: Two-Wire Serial Register Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
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2
MT9D131
SIGNAL DESCRIPTION
TABLE 3. SIGNAL DESCRIPTION
Name
EXTCLK
RESET_BAR
STANDBY
TEST
SCLK
S
ADDR
D
OUT
0−D
OUT
7
FRAME_VALID
LINE_VALID
PIXCLK
S
DATA
V
DD
V
DD
PLL
V
AA
VAAPIX
V
DD
Q
V
DD
GPIO
A
GND
D
GND
Type
Input
Input
Input
Input
Input
Input
Output
Output
Output
Output
I/O
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Description
Master clock signal (can either drive the on-chip PLL or bypass it).
Master reset signal, active LOW.
Controls sensor’s standby mode.
Reserved for factory test. Tie to digital ground during normal operation.
Two-wire serial interface clock.
Selects device address for the two-wire serial interface. The address is
0x90 when S
ADDR
is tied LOW, 0xBA if tied HIGH. See also R0x0D:0[10].
Eight-bit image data output or most significant bits (MSB) of 10-bit sensor
bypass mode.
Identifies rows in the active image.
Identifies lines in the active image.
Pixel clock. To be used for sampling D
OUT
, FRAME_VALID, and
LINE_VALID.
Two-wire serial interface data.
Digital power (1.8V).
PLL power (2.8V).
Analog power (2.8V).
Pixel array power (2.8V).
I/O power (nominal 1.8V or 2.8V).
I/O power for GPIO (nominal 1.8V or 2.8V).
Analog ground.
Digital, I/O, and PLL ground.
1
1
1
1
Note
1. 1. See “Standby Hardware Configuration”.
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5
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