lQ
QT60160, QT60240
16
AND
24 K
EY
QM
ATRIX
™ T
OUCH
S
ENSOR
IC
s
SCL
/RST
Y0A
Y2B
SMP
SDA
Y1A
Y2A
These devices are designed for low cost mobile and consumer electronics
applications.
QMatrix™ technology employs transverse charge-transfer sensing electrode
designs which can be made very compact and are easily wired. Charge is
forced from an emitting electrode into the overlying panel dielectric, and then
collected on a receiver electrode which directs the charge into a sampling
capacitor which is then converted directly to digital form without the use of
amplifiers.
Keys are configured in a matrix format that minimizes the number of required
scan lines and device pins. The key electrodes can be designed into a
conventional Printed Circuit Board (PCB) or Flexible Printed Circuit Board
(FPCB) as a copper pattern, or as printed conductive ink on plastic film.
M_SYNC
CHANGE
VSS
VDD
VSS
VDD
X6
X7
1
2
3
4
5
6
7
8
32 31 30 29 28 27 26 25
24
23
Y1B
Y0B
A0
VSS
VDD
A1
VDD
X5
QT60240
QT60160
MLF-32
22
21
20
19
18
17
9 10 11 12 13 14 15 16
X1
X0
S_SYNC
VREF
LATCH
X4
X3
X2
AT A GLANCE
Number of keys:
Technology:
Key outline sizes:
Key spacings:
Electrode design:
Layers required:
Panel materials:
Adjacent Metal:
Panel thickness:
Key sensitivity:
Interface:
Power:
Package:
Signal processing:
Applications:
1 to 16 (QT60160), or 1 to 24 (QT60240)
Patented spread-spectrum charge-transfer (transverse mode)
6mm x 6mm or larger (panel thickness dependent); widely different sizes and shapes possible
8mm or wider, center to center (panel thickness dependent)
Two-part electrode shapes (drive-receive); wide variety of possible layouts
One layer (with jumpers), two layers (no jumpers)
Plastic, glass, composites, painted surfaces (low particle density metallic paints possible)
Compatible with grounded metal immediately next to keys
Up to 50mm glass, 20mm plastic (key size dependent)
Individually settable via simple commands over serial interface
I
2
C slave mode (100kHz), or parallel output via external shift registers
1.8V ~ 5.5V, 40µA (16 keys at 1.8V, 2s Low Power mode). Guaranteed to 1.62V.
32-pin 5 x 5mm MLF RoHS compliant
Self-calibration, auto drift compensation, noise filtering, Adjacent Key Suppression
Mobile phones, remote controls, domestic appliances, PC peripherals, automotive
TM
Electrode materials:
PCB, FPCB, silver or carbon on film, ITO on film, Orgacon
†
ink on film
Moisture tolerance:
Best in class.
†
Orgacon is a registered tra demark of Agfa-Gevaert N.V
AVAILABLE OPTIONS
Part Number
QT60160-ISG
QT60240-ISG
Keys
16
24
T
A
-40 C to +85
0
C
-40
0
C to +85
0
C
0
LQ
Copyright © 2006 QRG Ltd
QT60240-ISG R8.06/0906
Contents
...............................
3
1.1 Introduction
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
1.2 Part Differences
. . . . . . . . . . . . . . . . . . . . . . . . . .
3
1.3 Enabling / Disabling Keys
. . . . . . . . . . . . . . . . . . . . .
3
2 Hardware and Functional
. . . . . . . . . . . . . . . . . . . . .
3
2.1 Matrix Scan Sequence
. . . . . . . . . . . . . . . . . . . . . . .
3
2.2 Burst Paring
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
2.3 Cs Sample Capacitor Operation
. . . . . . . . . . . . . . . . . .
3
2.4 Sample Capacitor Saturation
...................
4
2.5 Sample Resistors
. . . . . . . . . . . . . . . . . . . . . . . . .
4
2.6 Signal Levels
. . . . . . . . . . . . . . . . . . . . . . . . . . .
4
2.7 Matrix Series Resistors
. . . . . . . . . . . . . . . . . . . . . .
5
2.8 Key Design
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
2.9 PCB Layout, Construction
. . . . . . . . . . . . . . . . . . . . .
6
2.9.1 Overview
...........................
6
2.9.2 LED Traces and Other Switching Signals
..............
6
2.9.3 PCB Cleanliness
........................
6
2.10 Power Supply Considerations
..................
6
2.11 Startup / Calibration Times
. . . . . . . . . . . . . . . . . . . .
7
2.12 Reset Input
...........................
7
2.13 Spread Spectrum Acquisitions
. . . . . . . . . . . . . . . . . .
7
2.14 Detection Integrators
. . . . . . . . . . . . . . . . . . . . . . .
7
2.15 Sleep
..............................
7
2.16 Wiring
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8
3 Interfaces
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10
3.1 Introduction
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
10
3.2 Shift Register Output Mode
. . . . . . . . . . . . . . . . . . . .
10
3.3 I2C Port
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10
3.4 CHANGE Pin
. . . . . . . . . . . . . . . . . . . . . . . . . . .
11
4 Control Commands
. . . . . . . . . . . . . . . . . . . . . . . .
12
4.1 Introduction
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
12
4.2 Writing Data to the Device
. . . . . . . . . . . . . . . . . . . . .
12
4.3 Reading Data From the Device
. . . . . . . . . . . . . . . . . .
12
4.4 Report Detections for All Keys
. . . . . . . . . . . . . . . . . . .
12
4.5 Raw Data Commands
. . . . . . . . . . . . . . . . . . . . . . .
13
4.6 Cal All
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
4.7 Setups
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
1 Overview
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
15
. . . . . . . . . . . . . . . . . . . . . . . . . . .
15
5.2 Transferring Data Bits
. . . . . . . . . . . . . . . . . . . . . . .
15
5.3 START and STOP Conditions
. . . . . . . . . . . . . . . . . . .
15
5.4 Address Packet Format
. . . . . . . . . . . . . . . . . . . . . .
15
5.5 Data Packet Format
. . . . . . . . . . . . . . . . . . . . . . . .
15
5.6 Combining Address and Data Packets Into a Transmission
. . . .
16
6 Setups
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17
6.1 Introduction
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
17
6.2 Negative Threshold - NTHR
. . . . . . . . . . . . . . . . . . . .
17
6.3 Positive Threshold - PTHR
. . . . . . . . . . . . . . . . . . . .
17
6.4 Drift Compensation - NDRIFT, PDRIFT
. . . . . . . . . . . . . .
17
6.5 Detect Integrators - NDIL, FDIL
. . . . . . . . . . . . . . . . . .
18
6.6 Negative Recal Delay - NRD
. . . . . . . . . . . . . . . . . . . .
18
6.7 Positive Recalibration Delay - PRD
. . . . . . . . . . . . . . . .
18
6.8 Burst Length - BL
. . . . . . . . . . . . . . . . . . . . . . . . .
19
6.9 Adjacent Key Suppression - AKS
. . . . . . . . . . . . . . . . .
19
6.10 Oscilloscope Sync - SSYNC
. . . . . . . . . . . . . . . . . . .
19
6.11 Mains Sync - MSYNC
. . . . . . . . . . . . . . . . . . . . . .
19
6.12 Sleep Duration - SLEEP
. . . . . . . . . . . . . . . . . . . . .
20
6.13 Wake on Key Touch - WAKE
. . . . . . . . . . . . . . . . . . .
20
6.14 Awake Timeout - AWAKE
. . . . . . . . . . . . . . . . . . . .
20
6.15 Drift Hold Time - DHT
. . . . . . . . . . . . . . . . . . . . . .
20
6.16 Setups Block
. . . . . . . . . . . . . . . . . . . . . . . . . .
21
7 Specifications
. . . . . . . . . . . . . . . . . . . . . . . . . . .
23
7.1 Absolute Maximum Electrical Specifications
. . . . . . . . . . . .
23
7.2 Recommended Operating Conditions
. . . . . . . . . . . . . . .
23
7.3 DC Specifications
. . . . . . . . . . . . . . . . . . . . . . . . .
23
7.4 Timing Specifications
. . . . . . . . . . . . . . . . . . . . . . .
23
7.5 Power Consumption
. . . . . . . . . . . . . . . . . . . . . . . .
24
7.6 Mechanical Dimensions
. . . . . . . . . . . . . . . . . . . . . .
25
7.7 Marking
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25
7.8 Moisture Sensitivity Level (MSL)
. . . . . . . . . . . . . . . . . .
25
5 I2C Operation
5.1 Interface Bus
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2
QT60240-ISG R8.06/0906
1 Overview
1.1 Introduction
QT60xx0 devices are digital burst mode charge-transfer (QT)
sensors designed specifically for matrix layout touch controls;
they include all signal processing functions necessary to
provide stable sensing under a wide variety of changing
conditions. Only a few external parts are required for
operation. The entire circuit can be built within a few square
centimeters of single-sided PCB area. CEM-1 and FR1
punched, single-sided materials can be used for the lowest
possible cost. The PCB’s rear can be mounted flush on the
back of a glass or plastic panel using a conventional
adhesive, such as 3M VHB two-sided adhesive acrylic film.
1.3 Enabling / Disabling Keys
The NDIL parameter is used to enable and disable keys in the
matrix. Setting NDIL = 0 for a key disables it (Section 6.5). At
no time can the number of enabled keys exceed the
maximum specified for the device (see Section 1.2).
On the QT60160, only the first 2 Y lines (Y0, Y1) are
operational by default. On the QT60160, to use keys located
on line Y2, one or more of the pre-enabled keys must be
disabled simultaneously while enabling the desired new keys.
This can be done in one Setups block load operation.
2 Hardware and Functional
2.1 Matrix Scan Sequence
The circuit operates by scanning each key sequentially, key
by key. Key scanning begins with location X=0 / Y=0 (key 0).
X axis keys are known as
rows
while Y axis keys are referred
to as
columns
although this has no reflection on actual wiring .
Keys are scanned sequentially by row, for example the
sequence X0Y0 X1Y0 .... X7Y0, X0Y1, X1Y1... etc. Keys are
also numbered from 0...23. Key 0 is located at X0Y0.
Table 2.1 shows the key numbering.
Table 2.1 Key Numbers
Y0
Y1
Y2
X7
7
15
23
X6
6
14
22
X5
5
13
21
X4
4
12
20
X3
3
11
19
X2
2
10
18
X1
1
9
17
X0
0
8
16
Key
numbers
Figure 1.1 Field Flow Between X and Y Elements
overlying panel
X
element
Y
elem ent
QT60xx0 devices employ transverse charge-transfer ('QT')
sensing, a technology that senses changes in electrical
charge forced across two electrode elements by a pulse edge
(Figure 1.1). QT60xx0 devices allow a wide range of key sizes
and shapes to be mixed together in a single touch panel.
The devices use an I
2
C interface to allow key data to be
extracted and to permit individual key parameter setup. The
command structure is designed to minimize the amount of
data traffic while maximizing the amount of information
conveyed.
In addition to normal operating and setup functions the device
can also report back actual signal strengths .
QmBtn™ software for the PC can be used to program the
operation of the IC, as well as read back key status and
signal levels in real time.
Each key is sampled in a burst of acquisition pulses whose
length is determined by the Setups parameter BL (page 19);
this can be set on a per-key basis. A burst is completed
entirely before the next key is sampled; at the end of each
burst the resulting signal is converted to digital form and
processed. The burst length directly impacts key gain; each
key can have a unique burst length in order to allow tailoring
of key sensitivity on a key-by-key basis.
2.2 Burst Paring
Keys that are disabled by setting NDIL = 0 (Section 6.5,
page 18) have their bursts removed from the scan sequence
to save scan time. As a consequence, the fewer keys that are
used the faster the device can respond. All calibration times
are reduced when keys
are
disabled
.
1.2 Part Differences
There are two versions of the device; one is capable of a
maximum of 16 keys (QT60160), the other is capable of a
maximum of 24 keys (QT60240).
These devices are identical in all respects, except for the
maximum number of keys specified. The keys can be located
anywhere within an electrical grid of 8 X and 3 Y scan lines.
Unused keys are always pared from the burst sequence in
order to optimize speed. Similarly, in a given part a lesser
number of enabled keys will cause any unused acquisition
burst timeslots to be pared from the sampling sequence to
optimize acquire speed. Thus, if only 14 keys are actually
enabled, only 14 timeslots are used for scanning.
2.3 Cs Sample Capacitor Operation
Cs capacitors absorb charge from the key electrodes on the
rising edge of each X pulse. On each falling edge of X, the Y
matrix line is clamped to ground to allow the electrode and
wiring charges to neutralize in preparation for the next pulse.
With each X pulse charge accumulates on Cs causing a
staircase increase in its differential voltage.
After the burst completes, the device clamps the Y line to
ground causing the opposite terminal to go negative. The
charge on Cs is then measured using an external resistor to
ramp the negative terminal upwards until a zero crossing is
achieved. The time required to zero cross becomes the
measurement result.
lQ
3
QT60240-ISG R8.06/0906
The Cs should be connected as shown in Figure 2.7, page 9.
The value of these capacitors is not critical but 4.7nF is
recommended for most cases. They should be 10 percent
X7R ceramics. If the transverse capacitive coupling from X to
Y is large enough the voltage on a Cs capacitor can saturate,
destroying gain. In such cases the burst length should be
reduced and/or the Cs value increased. See Section 2.4.
If a Y line is not used its corresponding Cs capacitor may be
omitted and the pins left floating.
Figure 2.1 VCs - Nonlinear During Burst
(Burst too long, or Cs too small, or X-Y transcapacitance too large)
X Drive
YnB
2.4 Sample Capacitor Saturation
Cs voltage saturation at a pin YnB is shown in Figure 2.1
Saturation begins to occur when the voltage at a YnB pin
becomes more negative than -0.25V at the end of the burst.
This nonlinearity is caused by excessive voltage
accumulation on Cs inducing conduction in the pin protection
diodes. This badly saturated signal destroys key gain and
introduces a strong thermal coefficient which can cause
'phantom' detection. The cause of this is either from the burst
length being too long, the Cs value being too small, or the
X-Y transfer coupling being too large. Solutions include
loosening up the key structure interleaving, more separation
of the X and Y lines on the PCB, increasing Cs, and
decreasing the burst length.
Increasing Cs will make the part slower; decreasing burst
length will make it less sensitive. A better PCB layout and a
looser key structure (up to a point) have no negative effects.
Cs voltages should be observed on an oscilloscope with the
matrix layer bonded to the panel material; if the Rs side of
any Cs ramps more negative than -0.25 volts during any burst
(not counting overshoot spikes which are probe artifacts),
there is a potential saturation problem.
Figure 2.2 shows a defective waveform similar to that of 2.1,
but in this case the distortion is caused by excessive stray
capacitance coupling from the Y line to AC ground ; for
example, from running too near and too far alongside a
ground trace, ground plane, or other traces. The excess
coupling causes the charge-transfer effect to dissipate a
significant portion of the received charge from a key into the
stray capacitance. This phenomenon is more subtle; it can be
best detected by increasing BL to a high count and watching
what the waveform does as it descends towards and below
-0.25V. The waveform will appear deceptively straight, but it
will slowly start to flatten even before the -0.25V level is
reached.
A correct waveform is shown in Figure 2.3. Note that the
bottom edge of the bottom trace is substantially straight
(ignoring the downward spikes).
Unlike other QT circuits, the Cs capacitor values on QT60xx 0
devices have no effect on conversion gain. However , they do
affect conversion time.
Unused Y lines should be left open.
Figure 2.2 VCs - Poor Gain, Nonlinear During Burst
(Excess capacitance from Y line to Gnd)
X Drive
YnB
Figure 2.3 VCs - Correct
X Drive
YnB
Figure 2.4 X-Drive Pulse Roll-off and Dwell Time
The Dwell time is fixed at ~500ns - see Section 2.7
X drive
Lost charge due to
inadequate settling
before end of dwell time
Dwell time
Y gate
2.6 Signal Levels
Quantum’s QmBtn software makes it is easy to observe the
absolute level of signal received by the sensor on each key.
The signal values should normally be in the range of 200 to
750 counts with properly designed key shapes and values of
Rs. However, long adjacent runs of X and Y lines can also
artificially boost the signal values, and induce signal
saturation; this is to be avoided. The X-to-Y coupling should
come mostly from intra-key electrode coupling, not from stray
X-to-Y trace coupling.
2.5 Sample Resistors
There are three sample resistors (Rs) used to perform
single-slope ADC conversion of the acquired charge on each
Cs capacitor. These resistors directly control acquisition gain;
larger values of Rs will proportionately increase signal gain.
For most applications Rs should be 1M
✡.
Unused Y lines do
not require an Rs resistor.
lQ
4
QT60240-ISG R8.06/0906
Figure 2.5 Probing X-Drive
Waveforms With a Coin
Figure 2.6 Recommended Key Structure
‘T’ should ideally be similar to the complete thickness the fields
need to penetrate to the touch surface. Smaller dimensions will also
work but will give less signal strength. If in doubt, make the pattern
coarser. The lower figure shows a simpler structure used for
compact key layouts, for example for mobile phones. A layout with a
common X drive and three receive electrodes is depicted.
Y0
X0
QmBtn software is available free of charge on Quantum’s
website www.qprox.com.
The signal swing from the smallest finger touch should
preferably exceed 8 counts, with 12 being a reasonable
target. The signal threshold setting (NTHR) should be set to a
value guaranteed to be less than the signal swing caused by
the smallest touch.
Increasing the burst length (BL) parameter will increase the
signal strengths as will increasing the sampling resistor (Rs)
values.
Y1
Y2
2.7 Matrix Series Resistors
The X and Y matrix scan lines can use series resistors
(referred to as Rx and Ry respectively) for improved EMC
performance (Figure 2.7, page 9).
X drive lines require Rx in most cases to reduce edge rates
and thus reduce RF emissions. Typical values range from
1K
✡
to 20K
✡
.
Y lines need Ry to reduce EMC susceptibility problems and in
some extreme cases, ESD. Typical Y values are about 1K
✡
.
Y resistors act to reduce noise susceptibility problems by
forming a natural low-pass filter with the Cs capacitors.
It is essential that the Rx and Ry resistors and Cs capacitors
be placed very close to the chip. Placing these parts more
than a few millimeters away opens the circuit up to high
frequency interference problems (above 20MHz) as the trace
lengths between the components and the chip start to act as
RF antennae.
The upper limits of Rx and Ry are reached when the signal
level and hence key sensitivity are clearly reduced. The limits
of Rx and Ry will depend on key geometry and stray
capacitance, and thus an oscilloscope is required to
determine optimum values of both.
Dwell time
is the duration in which charge coupled from X to
Y is captured (Figure 2.4, page 4). Increasing Rx values will
cause the leading edge of the X pulses to increasingly roll off,
causing the loss of captured charge (and hence loss of signal
strength) from the keys.
The dwell time of these parts is fixed at 500ns. If the X pulses
have not settled within 500ns, key gain will be reduced; if this
happens, either the stray capacitance on the X line(s) should
be reduced (by a layout change, for example by reducing X
line exposure to nearby ground planes or traces), or, the Rx
resistor needs to be reduced in value (or a combination of
both approaches).
lQ
5
QT60240-ISG R8.06/0906
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