SE97B
DDR memory module temp sensor with integrated SPD
Rev. 01 — 27 January 2010
Product data sheet
1. General description
Meets JEDEC Specification 42.4 TSE2002B1, 3 Jun 2009. The NXP Semiconductors
SE97B measures temperature from
−40 °C
to +125
°C
with JEDEC Grade B
±1 °C
maximum accuracy between +75
°C
and +95
°C
critical zone and also provide 256 bytes
of EEPROM memory communicating via the I
2
C-bus/SMBus. It is typically mounted on a
DDR3 Dual In-Line Memory Module (DIMM) measuring the DRAM temperature in
accordance with the new JEDEC (JC-42.4)
Mobile Platform Memory Module Temperature
Sensor Component
specification and also replacing the Serial Presence Detect (SPD)
which is used to store memory module and vendor information.
The SE97B thermal sensor and EEPROM operates over the V
DD
range of 3.0 V to 3.6 V.
The TS consists of a
ΔΣ
Analog to Digital Converter (ADC) that monitors and updates its
own temperature readings 10 times per second, converts the reading to a digital data, and
latches them into the data temperature register. User-programmable registers, the
specification of upper/lower alarm and critical temperature trip points, EVENT output
control, and temperature shutdown, provide flexibility for DIMM temperature-sensing
applications.
When the temperature changes beyond the specified boundary limits, the SE97B outputs
an EVENT signal using an open-drain output that can be pulled up between 0.9 V and
3.6 V. The user has the option of setting the EVENT output signal polarity as either an
active LOW or active HIGH comparator output for thermostat operation, or as a
temperature event interrupt output for microprocessor-based systems. The EVENT output
can also be configured as only a critical temperature output.
The EEPROM is designed specifically for DRAM DIMMs SPD. The lower 128 bytes
(address 00h to 7Fh) can be Permanent Write Protected (PWP) or Reversible Write
Protected (RWP) by software. This allows DRAM vendor and product information to be
stored and write protected. The upper 128 bytes (address 80h to FFh) are not write
protected and can be used for general purpose data storage.
The SE97B has a single die for both the temp sensor and EEPROM for higher reliability
and supports the industry-standard 2-wire I
2
C-bus/SMBus serial interface. The SMBus
TIMEOUT function is supported to prevent system lock-ups. Manufacturer and Device ID
registers provide the ability to confirm the identity of the device. Three address pins allow
up to eight devices to be controlled on a single bus.
The SE98B is available as the SE97B thermal sensor only.
NXP Semiconductors
SE97B
DDR memory module temp sensor with integrated SPD
Table 1.
Feature
Comparison of SE97 versus SE97B features
SE97
old JEDEC specification
no SMBus Timeout
SMBus Timeout 25 ms to 35 ms
400 kHz
V
IL(max)
= 0.3
×
V
DD
; V
IH(min)
= 0.7
×
V
DD
set to 0
frozen
set to 0
yes
set to 0
50 ns
-
1010 0010
0000 0001
Grade B
0.6 V
3.0 V to 3.6 V
3.0 V to 3.6 V
1.7 V to 3.6 V
assembly plant Hong Kong
3.0 V to 3.6 V
assembly plant Bangkok
(thicker die and leadframe)
0000 0011
Improved Grade B
1.8 V
0.05
×
V
DD
set to 1
set to 1
de-assert
set to 1
SE97B
new JEDEC specification
SMBus Timeout 25 ms to 35 ms
JEDEC specification
Bit 8 ‘1’ Thermal Sensor shutdown
Bit 8 ‘0’ Thermal Sensor active
I
2
C-bus maximum frequency
I
2
C SCL and SDA V
IL
/V
IH
voltage levels
Capabilities bit 6 SMBus Timeout
EVENT pin operation
Capabilities bit 7 EVENT pin
A0 pin is 10 V tolerant
Capabilities bit 5 VHV
I
2
C spike suppression
I
2
C input hysteresis
SE97 Device ID register
Revision ID register
Temperature Sensor accuracy
Power-On Reset (POR)
Temperature Sensor voltage range
EEPROM Write voltage range
EEPROM Read voltage range
2 mm
×
3 mm
×
0.8 mm package
2. Features
2.1 General features
JEDEC (JC-42.4) DIMM temperature sensor plus 256-byte serial EEPROM for Serial
Presence Detect (SPD)
SDA open-drain output design for best operation in distributed multi-point applications
Shutdown current: 0.1
μA
(typ.) and 5.0
μA
(max.)
Power-on reset: 1.8 V (typ.)
2-wire interface: I
2
C-bus/SMBus compatible, 0 Hz to 400 kHz
SMBus Alert Response Address and TIMEOUT 25 ms to 35 ms (programmable)
ESD protection exceeds 2500 V HBM per JESD22-A114, 250 V MM per
JESD22-A115, and 1000 V CDM per JESD22-C101
Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
Available in HWSON8 package
2.2 Temperature sensor features
11-bit ADC Temperature-to-Digital converter with 0.125
°C
resolution
Voltage range: 3.0 V to 3.6 V
Operating current: 250
μA
(typ.) and 400
μA
(max.)
SE97B_1
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 27 January 2010
2 of 53
NXP Semiconductors
SE97B
DDR memory module temp sensor with integrated SPD
Programmable hysteresis threshold: off, 0
°C,
1.5
°C,
3
°C,
6
°C
Over/under/critical temperature EVENT output
B-grade accuracy:
±0.5 °C/±1 °C
(typ./max.)
→
+75
°C
to +95
°C
±1.0 °C/±2 °C
(typ./max.)
→
+40
°C
to +125
°C
±2.0 °C/±3 °C
(typ./max.)
→ −40 °C
to +125
°C
2.3 Serial EEPROM features
Read and write voltage range: 3.0 V to 3.6 V
Operating current:
Write
→
0.6 mA (typ.) for 3.5 ms (typ.)
Read
→
100
μA
(typ.)
Organized as 1 block of 256 bytes (256
×
8)
100,000 write/erase cycles and 10 years of data retention
Permanent and Reversible Software Write Protect
Software Write Protection for the lower 128 bytes
3. Applications
DDR2 and DDR3 memory modules
Laptops, personal computers and servers
Enterprise networking
Hard disk drives and other PC peripherals
4. Ordering information
Table 2.
Ordering information
Topside
mark
97B
Package
Name
HWSON8
Description
plastic thermal enhanced very very thin small outline package;
no leads; 8 terminals; body 2
×
3
×
0.8 mm
Version
SOT1069-2
Type number
SE97BTP
[1]
[1]
Industry standard 2 mm
×
3 mm
×
0.8 mm package to JEDEC WCE-3, PSON8 in 8 mm
×
4 mm pitch tape 4 k quantity reels.
SE97B_1
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 27 January 2010
3 of 53
NXP Semiconductors
SE97B
DDR memory module temp sensor with integrated SPD
5. Block diagram
SE97B
TEMPERATURE REGISTER
CRITICAL ALARM TRIP
UPPER ALARM TRIP
LOWER ALARM TRIP
CAPABILITY
MANUFACTURING ID
DEVICE/REV ID
SMBus TIMEOUT/ALERT
CONFIGURATION
•
•
•
•
•
•
•
HYSTERESIS
SHUTDOWN TEMP SENSOR
LOCK PROTECTION
EVENT OUTPUT ON/OFF
EVENT OUTPUT POLARITY
EVENT OUTPUT STATUS
CLEAR EVENT OUTPUT STATUS
FFh
POR
BAND GAP
TEMPERATURE
SENSOR
11-BIT
ΔΣ
ADC
V
DD
V
SS
EVENT
SMBus/I
2
C-BUS
INTERFACE
FILTER
SCL
SDA
2-kbit EEPROM
NO
WRITE PROTECT
80h
7Fh
SOFTWARE
WRITE PROTECT
00h
10 V
OVERVOLTAGE
R
30 kΩ to 800 kΩ
A0
A1
R
30 kΩ to 800 kΩ
A2
R
30 kΩ to 800 kΩ
POINTER REGISTER
002aae309
Fig 1.
Block diagram of SE97B
SE97B_1
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 27 January 2010
4 of 53
NXP Semiconductors
SE97B
DDR memory module temp sensor with integrated SPD
6. Pinning information
6.1 Pinning
terminal 1
index area
A0
A1
A2
V
SS
1
2
8
7
V
DD
EVENT
SCL
SDA
SE97BTP
3
4
6
5
002aae311
Transparent top view
Fig 2.
Pin configuration for HWSON8
6.2 Pin description
Table 3.
Symbol
A0
A1
A2
V
SS
SDA
SCL
EVENT
V
DD
Pin description
Pin
1
2
3
4
5
6
7
8
Type
I
I
I
ground
I/O
I
O
power
Description
I
2
C-bus/SMBus slave address bit 0 with internal pull-down. This
input is overvoltage tolerant to support software write protection.
I
2
C-bus/SMBus slave address bit 1 with internal pull-down
I
2
C-bus/SMBus slave address bit 2 with internal pull-down
device ground
SMBus/I
2
C-bus serial data input/output (open-drain). Must have
external pull-up resistor.
SMBus/I
2
C-bus serial clock input/output (open-drain). Must have
external pull-up resistor.
Thermal alarm output for high/low and critical temperature limit
(open-drain). Must have external pull-up resistor.
device power supply (3.0 V to 3.6 V)
SE97B_1
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 27 January 2010
5 of 53
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