NC7WZ240 TinyLogic UHS Dual Inverting Buffer with 3-STATE Outputs
March 2001
Revised January 2005
NC7WZ240
TinyLogic
UHS Dual Inverting Buffer
with 3-STATE Outputs
General Description
The NC7WZ240 is a Dual Inverting Buffer with indepen-
dent active LOW enables for the 3-STATE outputs. The
Ultra High Speed device is fabricated with advanced
CMOS technology to achieve superior switching perfor-
mance with high output drive while maintaining low static
power dissipation over a broad V
CC
operating range. The
device is specified to operate over the 1.65V to 5.5V V
CC
operating range. The inputs and outputs are high imped-
ance when V
CC
is 0V. Inputs tolerate voltages up to 5.5V
independent of V
CC
operating range. Outputs tolerate volt-
ages above V
CC
when in the 3-STATE condition.
Features
s
Space saving US8 surface mount package
s
MicroPak
Pb-Free leadless package
s
Ultra High Speed; t
PD
2.3 ns typ into 50 pF at 5V V
CC
s
High Output Drive;
±
24 mA at 3V V
CC
s
Broad V
CC
Operating Range: 1.65V to 5.5V
s
Matches the performance of LCX when operated at
3.3V V
CC
s
Power down high impedance inputs/outputs
s
Overvoltage tolerant inputs facilitate 5V to 3V translation
s
Outputs are overvoltage tolerant in 3-STATE mode
s
Patented noise/EMI reduction circuitry implemented
Ordering Code:
Product
Order
Number
NC7WZ240L8X
Package
Number
MAC08A
Code
Top Mark
WZ40
U7
8-Lead US8, JEDEC MO-187, Variation CA 3.1mm Wide 3k Units on Tape and Reel
Pb-Free 8-Lead MicroPak, 1.6 mm Wide
5k Units on Tape and Reel
Package Description
Supplied As
NC7WZ240K8X MAB08A
Pb-Free package per JEDEC J-STD-020B.
TinyLogic is a registered trademark of Fairchild Semiconductor Corporation.
MicroPak is a trademark of Fairchild Semiconductor Corporation.
© 2005 Fairchild Semiconductor Corporation
DS500398
www.fairchildsemi.com
NC7WZ240
Logic Symbol
IEEE/IEC
Connection Diagrams
Pin Assignments for US8
Pin Descriptions
Pin Names
OE
n
A
n
Y
n
Description
Enable Inputs for 3-STATE Outputs
Inputs
3-STATE Outputs
(Top View)
Pin One Orientation Diagram
Function Table
Inputs
OE
L
L
H
H
H
=
HIGH Logic Level
Output
A
n
L
H
L
H
L
=
LOW Logic Level
Y
n
H
L
Z
Z
Z
=
3-STATE
AAA represents Product Code Top Mark - see ordering code
Note:
Orientation of Top Mark determines Pin One location. Read the top
product code mark left to right, Pin One is the lower left pin (see diagram).
Pad Assignment for MicroPak
(Top Through View)
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2
NC7WZ240
Absolute Maximum Ratings
(Note 1)
Supply Voltage (V
CC
)
DC Input Voltage (V
IN
) (Note 2)
DC Output Voltage (V
OUT
)
DC Input Diode Current (I
IK
)
@V
IN
<
0V
DC Output Diode Current (I
OK
)
@V
OUT
<
0V
DC Output Source/Sink Current (I
OUT
)
DC V
CC
/Ground Current (I
CC
/I
GND
)
Storage Temperature Range (T
STG
)
Junction Lead Temperature under Bias (T
J
)
Junction Lead Temperature (T
L
)
(Soldering, 10 seconds)
Power Dissipation (P
D
) @
+
85
°
C
−
0.5V to
+
7.0V
−
0.5V to
+
7.0V
−
0.5V to
+
7.0V
−
50 mA
−
50 mA
±
50 mA
±
100 mA
−
65
°
C to
+
150
°
C
+
150
°
C
+
260
°
C
250 mW
Recommended Operating
Conditions
(Note 3)
Supply Voltage Operating (V
CC
)
Supply Voltage Data Retention (V
CC
)
Input Voltage (V
IN
)
Output Voltage (V
OUT
)
Active State
3-STATE
Operating Temperature (T
A
)
Input Rise and Fall Time (t
r
, t
f
)
V
CC
@ 1.8V, 0.15V, 2.5V
±
0.2V
V
CC
@ 3.3V
±
0.3V
V
CC
@ 5.0V
±
0.5V
Thermal Resistance (
θ
JA
)
0 ns/V to 20 ns/V
0 ns/V to 10 ns/V
0 ns/V to 5 ns/V
250
°
C/W
0V to V
CC
0V to 5.5V
1.65V to 5.5V
1.5V to 5.5V
0V to 5.5V
−
40
°
C to
+
85
°
C
Note 1:
Absolute maximum ratings are DC values beyond which the device
may be damaged or have its useful life impaired. The datasheet specifica-
tions should be met, without exception, to ensure that the system design is
reliable over its power supply, temperature, and output/input loading vari-
ables. Fairchild does not recommend operation outside datasheet specifi-
cations.
Note 2:
The input and output negative voltage ratings may be exceeded if
the input and output diode current ratings are observed.
Note 3:
Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
OH
Parameter
HIGH Level Input Voltage
LOW Level Input Voltage
HIGH Level Output Voltage
V
CC
(V)
2.3 to 5.5
1.65 to 1.95
2.3 to 5.5
1.65
2.3
3.0
4.5
1.65
2.3
3.0
3.0
4.5
V
OL
LOW Level Output Voltage
1.65
2.3
3.0
4.5
1.65
2.3
3.0
3.0
4.5
I
IN
I
OZ
I
OFF
I
CC
Input Leakage Current
3-STATE Output Leakage
Power Off Leakage Current
Quiescent Supply Current
0 to 5.5
1.65 to 5.5
0.0
1.65 to 5.5
1.55
2.2
2.9
4.4
1.29
1.9
2.4
2.3
3.8
1.65
2.3
3.0
4.5
1.52
2.15
2.80
2.68
4.20
0.0
0.0
0.0
0.0
0.08
0.10
0.15
0.22
0.22
0.10
0.10
0.10
0.10
0.24
0.3
0.4
0.55
0.55
±0.1
±0.5
1
1
Min
0.7 V
CC
0.25 V
CC
0.3 V
CC
1.55
2.2
2.9
4.4
1.29
1.9
2.4
2.3
3.8
0.10
0.10
0.10
0.10
0.24
0.3
0.4
0.55
0.55
±1
±5
10
10
µA
µA
µA
µA
V
I
OL
=
4 mA
I
OL
=
8 mA
I
OL
=
16 mA
I
OL
=
24 mA
I
OL
=
32 mA
V
IN
=
5.5V, GND
V
IN
=
V
IH
or V
IL
0
≤
V
OUT
≤
5.5V
V
IN
or V
OUT
=
5.5V
V
IN
=
5.5V, GND
V
V
IN
=
V
IH
I
OL
=
100
µA
or V
IL
V
or V
IL
I
OH
= −4
mA
V
IN
=
V
IH
I
OH
= −8
mA
I
OH
= −16
mA
I
OH
= −24
mA
I
OH
= −32
mA
V
V
IN
=
V
IH
I
OH
= −100 µA
or V
IL
1.65 to 1.95 0.75 V
CC
T
A
= +25°C
Typ
Max
T
A
= −40°C
to
+85°C
Min
0.75 V
CC
0.7 V
CC
0.25 V
CC
0.3 V
CC
Max
Units
V
V
Conditions
3
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NC7WZ240
Noise Characteristics
Symbol
Parameter
V
CC
(V)
5.0
5.0
5.0
5.0
5.0
T
A
= +
25°C
Typ
Max
1.0
1.0
4.0
3.5
1.5
Units
V
V
V
V
V
Conditions
C
L
=
50 pF
C
L
=
50 pF
C
L
=
50 pF
C
L
=
50 pF
C
L
=
50 pF
V
OLP
(Note 4) Quiet Output Maximum Dynamic V
OL
V
OLV
(Note 4) Quiet Output Minimum Dynamic V
OL
V
OHV
(Note 4) Quiet Output Minimum Dynamic V
OH
V
IHD
(Note 4)
V
ILD
(Note 4)
Minimum HIGH Level Dynamic Input Voltage
Maximum LOW Level Dynamic Input Voltage
Note 4:
Parameter guaranteed by design.
AC Electrical Characteristics
Symbol
t
PLH
,
t
PHL
Parameter
Propagation Delay
A
n
to Y
n
V
CC
(V)
1.8
±
0.15
2.5
±
0.2
3.3
±
0.3
5.0
±
0.5
t
PLH,
t
PHL
t
OSLH
,
t
OSHL
t
PZL
,
t
PZH
Propagation Delay
A
n
to Y
n
Output to Output Skew
(Note 5)
Output Enable Time
3.3
±
0.3
5.0
±
0.5
3.3
±
0.3
5.0
±
0.5
1.8
±
0.15
2.5
±
0.2
3.3
±
0.3
5.5
±
0.5
t
PLZ
,
t
PHZ
Output Disable Time
1.8
±
0.15
2.5
±
0.2
3.3
±
0.3
5.0
±
0.5
C
IN
C
OUT
C
PD
Input Capacitance
Output Capacitance
Power Dissipation Capacitance
0
5.0
3.3
5.0
3.0
1.8
1.2
0.8
2.5
1.5
0.8
0.3
2.5
4
10
12
Min
2.0
1.0
0.8
0.5
1.2
0.8
T
A
= +25°C
Typ
Max
12.0
7.5
5.2
4.5
5.7
5.0
1.0
0.8
14.0
8.5
6.2
5.5
12.0
8.0
5.7
4.7
3.0
1.8
1.2
0.8
2.5
1.5
0.8
0.3
T
A
= −40°C
to
+85°C
Min
2.0
1.0
0.8
0.5
1.2
0.8
Max
13.0
8.0
5.5
4.8
6.0
5.3
1.0
0.8
15.0
9.0
6.5
5.8
13.0
8.5
6.0
5.0
ns
ns
ns
ns
C
L
=
50 pF
R
D
=
500Ω
S1= Open
C
L
=
50 pF
R
D
=
500Ω
S1= Open
C
L
=
50 pF
R
D
, R
U
=
500
Ω
S1
=
GND for t
PZH
S1
=
V
I
for t
PZL
V
I
=
2 x V
CC
C
L
=
50 pF
R
D
, R
U
=
500
Ω
S1
=
GND for t
PZH
S1
=
V
I
for t
PZL
V
I
=
2 x V
CC
pF
pF
(Note 6)
Figure 2
Figures
1, 3
Figures
1, 3
Figures
1, 3
Figures
1, 3
ns
Units
Conditions
C
L
=
15 pF
R
D
=
1 MΩ
S1= Open
Figures
1, 3
Figure
Number
Note 5:
Parameter guaranteed by design. t
OSLH
=
|t
PLHmax
−
t
PLHmin
|; t
OSHL
=
|t
PHLmax
−
t
PHLmin
|.
Note 6:
C
PD
is defined as the value of the internal equivalent capacitance which is derived from dynamic operating current consumption (I
CCD
) at no output
loading and operating at 50% duty cycle. (See Figure 2.) C
PD
is related to I
CCD
dynamic operating current by the expression:
I
CCD
=
(C
PD
)(V
CC
)(f
IN
)
+
(I
CC
static).
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4
NC7WZ240
AC Loading and Waveforms
C
L
includes load and stray capacitance
Input PRR
=
1.0 MHz; t
w
=
500 ns
FIGURE 1. AC Test Circuit
Input
=
AC Waveform; t
r
=
t
f
=
1.8 ns;
PRR
=
10 MHz; Duty Cycle
=
50%
FIGURE 2. I
CCD
Test Circuit
FIGURE 3. AC Waveforms
5
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