LTC1669
10-Bit Rail-to-Rail
Micropower DAC with I
2
C Interface
FEATURES
s
s
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s
DESCRIPTIO
s
s
s
s
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s
Micropower 10-Bit DAC in SOT-23
Low Operating Current: 60µA
Ultralow Power Shutdown Mode: 12µA
2-Wire Serial Interface Compatible
with I
2
C
TM
Selectable Internal Reference or Ratiometric to V
CC
Maximum DNL Error: 0.75LSB
8 User Selectable Addresses (MSOP Package)
Single 2.7V to 5.5V Operation
Buffered True Rail-to-Rail Voltage Output
Power-On Reset
1.5V V
IL
and 2.1V V
IH
for SDA and SCL
Small 5-Lead SOT-23 and 8-Lead MSOP Packages
The LTC
®
1669 is a 10-bit voltage output DAC with true
buffered rail-to-rail output voltage capability. It operates
from a single supply with a range of 2.7V to 5.5V. The
reference for the DAC is selectable between the supply
voltage or an internal bandgap reference. Selecting the
internal bandgap reference will set the full-scale output
voltage range to 2.5V. Selecting the supply as the refer-
ence sets the output voltage range to the supply voltage.
The part features a simple 2-wire serial interface compat-
ible with I
2
C that allows communication between many
devices. The internal data registers are double buffered to
allow for simultaneous update of several devices at once.
The DAC can be put in low current power-down mode for
use in power conscious systems.
Power-on reset ensures the DAC output is at 0V when
power is initially applied, and all internal registers are
cleared. The LTC1669 is pin-for-pin compatible with the
LTC1663.
, LTC and LT are registered trademarks of Linear Technology Corporation.
I
2
C is a trademark of Philips Electronics N.V.
APPLICATIO S
s
s
s
s
s
s
Digital Calibration
Offset/Gain Adjustment
Industrial Process Control
Automatic Test Equipment
Arbitrary Function Generators
Battery-Powered Data Conversion Products
BLOCK DIAGRA
4 (5)
V
CC
1.25V
BANDGAP
REFERENCE
REFERENCE
SELECT
ERROR (LSB)
10-BIT
DAC LATCH
10-BIT BUFFERED V
OUT
DAC
MSOP
PACKAGE
ONLY
(6) AD0
(2) AD1
(3) AD2
2-WIRE INTERFACE
SDA
1 (1)
SCL
5 (4)
GND
2 (7)
1669 BD
V
OUT
3 (8)
COMMAND
LATCH
INPUT
LATCH
NOTE: PIN NUMBERS IN PARENTHESES REFER TO THE MSOP PACKAGE
1669f
U
Differential Nonlinearity (DNL)
1.0
0.8
0.6
0.4
0.2
0
– 0.2
– 0.4
– 0.6
– 0.8
–1.0
0
28
156 384 512 640 768 896 1024
CODE
1669 G02
W
U
V
REF
= V
CC
= 5V
T
A
= 25°C
1
LTC1669
ABSOLUTE
AXI U
RATI GS
V
CC
to GND .............................................. – 0.3V to 7.5V
SDA, SCL ..................................................– 0.3V to 7.5V
AD0, AD1, AD2 (MSOP Only) ...... – 0.3V to (V
CC
+ 0.3V)
V
OUT
............................................ – 0.3V to (V
CC
+ 0.3V)
PACKAGE/ORDER I FOR ATIO
TOP VIEW
SDA
AD1
AD2
SCL
1
2
3
4
8
7
6
5
V
OUT
GND
AD0
V
CC
ORDER PART
NUMBER
TOP VIEW
LTC1669CMS8
LTC1669IMS8
LTC1669-8CMS8
LTC1669-8IMS8
MS8 PACKAGE
8-LEAD PLASTIC MSOP
MS8 PART MARKING
LTAHV
LTAHX
LTAHT
LTAHU
T
JMAX
= 125°C,
θ
JA
= 150°C/W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
The
q
denotes specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. V
CC
= 2.7V to 5.5V, V
CC
set as reference, V
OUT
unloaded,
unless otherwise noted.
SYMBOL
DAC
Resolution
Monotonicity
DNL
INL
V
OS
V
OSTC
FSE
V
OUT
V
FSTC
PSRR
Differential Nonlinearity
Integral Nonlinearity
Offset Error
Offset Error Temperature Coefficient
Full-Scale Error
DAC Output Span
Full-Scale Voltage Temperature Coefficient
Power Supply Rejection Ratio
Reference Set to V
CC
Reference Set to Internal Bandgap
Reference Set to V
CC
Reference Set to Internal Bandgap
Reference Set to V
CC
Reference Set to Internal Bandgap
Reference Set to Internal Bandgap,
Code = 1023
q
q
q
q
ELECTRICAL CHARACTERISTICS
PARAMETER
CONDITIONS
(Note 2)
Guaranteed Monotonic (Note 2)
(Note 2)
Measured at Code 20
Power Supply
V
CC
I
CC
I
SD
Positive Supply Voltage
Supply Current
Supply Current in Shutdown Mode
Short-Circuit Current (Sourcing)
Short-Circuit Current (Sinking)
V
CC
= 3V (Note 3)
V
CC
= 5V (Note 3)
(Note 3)
V
OUT
Shorted to GND, Input Code = 1023
V
OUT
Shorted to V
CC
, Input Code = 0
2.7
60
75
12
25
30
5.5
100
125
24
100
120
V
µA
µA
µA
mA
mA
1669f
Op Amp DC Performance
q
q
2
U
U
W
W W
U
W
(Note 1)
Operating Temperature Range
LTC1669C .............................................. 0°C to 70°C
LTC1669I ........................................... – 40°C to 85°C
Storage Temperature Range ................ – 65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
ORDER PART
NUMBER
SDA 1
GND 2
V
OUT
3
4 V
CC
5 SCL
LTC1669CS5
LTC1669-1CS5
S5 PART MARKING
LTAHW
LTAHR
S5 PACKAGE
5-LEAD PLASTIC SOT-23
T
JMAX
= 125°C,
θ
JA
= 250°C/W
MIN
10
10
TYP
MAX
UNITS
Bits
Bits
q
q
q
q
±0.2
±0.5
±10
±15
±3
±3
0 to V
CC
0 to 2.5
±30
±50
±0.4
±0.75
±2.5
±30
±15
±15
LSB
LSB
mV
µV/°C
LSB
LSB
V
V
µV/°C
µV/°C
LSB/V
q
q
q
LTC1669
The
q
denotes specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. V
CC
= 2.7V to 5.5V, V
CC
set as reference, V
OUT
unloaded,
unless otherwise noted.
SYMBOL
PARAMETER
Output Impedance to GND
CONDITIONS
Input Code = 0, V
CC
= 5V
Input Code = 0, V
CC
= 3V
In Shutdown Mode
Input Code = 1023, V
CC
= 5V
Input Code = 1023, V
CC
= 3V
Rising (Notes 4, 5)
Falling (Notes 4, 5)
To
±0.5LSB
(Notes 4, 5)
1LSB Change Around Major Carry
q
q
ELECTRICAL CHARACTERISTICS
MIN
TYP
65
150
500
80
120
0.75
0.25
30
0.75
70
MAX
UNITS
Ω
Ω
kΩ
Ω
Ω
V/µs
V/µs
µs
nV • s
nV • s
V
Output Impedance to V
CC
AC Performance
Voltage Output Slew Rate
Voltage Output Settling Time
Digital Feedthrough
Digital-to-Analog Glitch Impulse
Digital Inputs SCL, SDA
V
IH
V
IL
V
LTH
I
LEAK
C
IN
V
OL
I
UP
V
IH
V
IL
High Level Input Voltage
Low Level Input Voltage
Logic Threshold Voltage
Digital Input Leakage
Digital Input Capacitance
Digital Output Low Voltage
Address Pin Pull-Up Current
High Level Input Voltage
Low Level Input Voltage
2.1
1.5
1.8
±1
10
0.4
0.5
1.5
0.8
V
V
µA
pF
V
µA
V
V
V
CC
= 5.5V and 0V, V
IN
= GND to V
CC
(Note 7)
I
PULLUP
= 3mA
V
IN
= 0V
q
q
q
q
q
V
CC
– 0.3
q
Digital Output SDA
Address Inputs AD0, AD1, AD2 (MSOP Only)
TI I G CHARACTERISTICS
SYMBOL
f
SCL
t
BUF
t
HD, STA
t
SU, STA
t
SU, STO
t
HD, DAT (IN)
t
HD, DAT (OUT)
t
SU, DAT
t
LOW
t
HIGH
t
f
t
r
PARAMETER
Clock Operating Frequency
Timing Characteristics (Notes 6, 7)
The
q
denotes specifications which apply over the full operating temperature
range, otherwise specifications are at T
A
= 25°C. V
CC
= 2.7V to 5.5V, V
CC
set as reference, V
OUT
unloaded, unless otherwise noted.
MIN
q
q
q
q
q
q
q
q
q
q
q
q
Note 1:
Absolute maximum ratings are those values beyond which the life
of a device may be impaired.
Note 2:
Nonlinearity and monotonicity are defined from code 20 to code
1003 (full scale). See Applications Information.
Note 3:
Digital inputs at 0V or V
CC
.
UW
TYP
MAX
100
UNITS
kHz
µs
µs
µs
µs
ns
Bus Free Time Between Stop and Start Condition
Hold Time After (Repeated) Start Condition
Repeated Start Condition Setup Time
Stop Condition Setup Time
Data Hold Time (Input)
Data Hold Time (Output)
Data Setup Time
Clock Low Period
Clock High Period
Clock, Data Fall Time
Clock, Data Rise Time
4.7
4
4.7
4
0
225
250
4.7
4
20
20
300
1000
500
3450
ns
ns
µs
µs
ns
ns
Note 4:
Load is 10kΩ in parallel with 100pF.
Note 5:
V
CC
= V
REF
= 5V. DAC switched between 0.1V
FS
and 0.9V
FS
,
i.e., codes k = 102 and k = 922.
Note 6:
All values are referenced to V
IH
and V
IL
levels.
Note 7:
Guaranteed by design and not subject to test.
1669f
3
LTC1669
TYPICAL PERFOR A CE CHARACTERISTICS
Integral Nonlinearity (INL)
1.0
0.8
0.6
0.4
ERROR (LSB)
ERROR (LSB)
V
REF
= V
CC
= 5V
T
A
= 25°C
0.4
0.2
0
– 0.2
– 0.4
– 0.6
– 0.8
–1.0
0
28
156 384 512 640 768 896 1024
CODE
1669 G01
OUTPUT VOLTAGE (V)
0.2
0
– 0.2
– 0.4
– 0.6
– 0.8
–1.0
Large-Signal Step Response
5
SDA
(VOLTS) 0
5
CODE = 990
4
V
OUT
(VOLTS) 2
1
CODE = 32
0
5µs/DIV
1669 G04
∆V
OUT
(LSB)
3
V
CC
= 5V
R
L
= 4.7k
C
L
= 100pF
T
A
= 25°C
Load Regulation vs Output Current
1.0
0.8
0.6
0.4
∆V
OUT
(LSB)
OFFSET ERROR VOLTAGE (mV)
2
1
0
–1
–2
–3
–4
–5
–60 –40 –20 0 20 40 60
TEMPERATURE (°C)
80
100
OUTPUT VOLTAGE (V)
V
CC
= V
REF
= 3V
V
OUT
= 1.5V
CODE = 512
T
A
= 25°C
0.2
0
SOURCE
SINK
– 0.2
– 0.4
– 0.6
– 0.8
–1.0
–1.0 – 0.8– 0.6– 0.4– 0.2 0 0.2 0.4 0.6 0.8 1.0
I
OUT
(mA)
1669 G07
4
U W
Differential Nonlinearity (DNL)
1.0
0.8
0.6
V
REF
= V
CC
= 5V
T
A
= 25°C
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
Source and Sink Current
Capability with V
CC
= 5V
T
A
= 25°C
DAC CODE = 1023
DAC CODE = 0
0
28
156 384 512 640 768 896 1024
CODE
1669 G02
0
0
1 2 3 4 5 6 7 8 9 10
OUTPUT CURRENT SOURCE/SINK (mA)
1669 G03
Midscale Glitch
1.0
5V
SDA
0V
CODE = 512 TO 511
0.8
0.6
0.4
0.2
0
Load Regulation vs Output Current
V
CC
= V
REF
= 5V
V
OUT
= 2.5V
CODE = 512
T
A
= 25°C
V
OUT
10mV/DIV
V
CC
= 5V
R
L
= 4.7k
C
L
= 100pF
T
A
= 25°C
2µs/DIV
1669 G05
– 0.2
– 0.4
– 0.6
– 0.8
–1.0
–4
–3
–2
–1 0
1
I
OUT
(mA)
2
3
4
SOURCE
SINK
1669 G06
Offset Error Voltage vs
Temperature
5
4
3
2.510
2.508
2.506
2.504
2.502
2.500
2.498
2.496
2.494
2.492
Full-Scale Output Voltage vs
Temperature
REFERENCE SET TO
INTERNAL BANDGAP
2.490
–60 –40 –20 0 20 40 60
TEMPERATURE (°C)
80
100
1669 G08
1669 G09
1669f
LTC1669
PIN FUNCTIONS
SDA (Pin 1, Pin 1 on SOT-23):
Serial Data Bidirectional
Pin. Data is shifted into the SDA pin and acknowledged by
the SDA pin. High impedance pin while data is shifted in.
Open-drain N-channel output during acknowledgment.
Requires a pull-up resistor or current source to V
CC
.
AD1 (Pin 2):
Slave Address Select Bit 1. Tie this pin to
either V
CC
or GND to modify the corresponding bit of the
LTC1669’s slave address.
AD2 (Pin 3):
Slave Address Select Bit 2. Tie this pin to
either V
CC
or GND to modify the corresponding bit of the
LTC1669’s slave address.
SCL (Pin 4, Pin 5 on SOT-23):
Serial Clock Input Pin. Data
is shifted into the SDA pin at the rising edges of the clock.
This high impedance pin requires a pull-up resistor or
current source to V
CC
.
V
CC
(Pin 5, Pin 4 on SOT-23):
Power Supply. 2.7V
≤
V
CC
≤
5.5V. Also used as the reference voltage input when the
part is programmed to use V
CC
as the reference.
AD0 (Pin 6):
Slave Address Select Bit 0. Tie this pin to
either V
CC
or GND to modify the corresponding bit of the
LTC1669’s slave address.
GND (Pin 7, Pin 2 on SOT-23):
System Ground.
V
OUT
(Pin 8, Pin 3 on SOT-23):
Voltage Output. Buffered
rail-to-rail DAC output.
DEFINITIONS
Differential Nonlinearity (DNL):
The difference between
the measured change and the ideal 1LSB change for any
two adjacent codes. The DNL error between any two codes
is calculated as follows:
DNL = (∆V
OUT
– LSB)/LSB
Where
∆V
OUT
is the measured voltage difference between
two adjacent codes.
Digital Feedthrough:
The glitch that appears at the analog
output caused by AC coupling from the digital inputs when
they change state. The area of the glitch is specified in
(nV)(sec).
Full-Scale Error (FSE):
The deviation of the actual full-
scale voltage from ideal. FSE includes the effects of offset
and gain errors (see Applications Information).
Integral Nonlinearity (INL):
The deviation from a straight
line passing through the endpoints of the DAC transfer
curve (Endpoint INL). Because the output cannot go below
zero, the linearity is measured between full scale and the
lowest code that guarantees the output will be greater than
zero. The INL error at a given input code is calculated as
follows:
INL = [V
OUT
– V
OS
– (V
FS
– V
OS
)(code/1023)]/LSB
Where V
OUT
is the output voltage of the DAC measured at
the given input code.
Least Significant Bit (LSB):
The ideal voltage difference
between two successive codes.
LSB = V
REF
/1024
Resolution (n):
Defines the number of DAC output states
(2
n
) that divide the full-scale range. Resolution does not
imply linearity.
Voltage Offset Error (V
OS
):
Nominally, the voltage at the
output when the DAC is loaded with all zeros. A single
supply DAC can have a true negative offset, but the output
cannot go below zero (see Applications Information).
For this reason, single supply DAC offset is measured at
the lowest code that guarantees the output will be greater
than zero.
U
U
U
U
U
1669f
5
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