NCP1232
Microprocessor Monitor
The NCP1232 is a fully–integrated processor supervisor. It provides
three important functions to safeguard processor functionality:
precision power on/off reset control, watchdog timer and external
reset override.
On power–up, the NCP1232 holds the processor in the reset state for
a minimum of 250 msec after VCC is within tolerance to ensure a
stable system start–up.
Microprocessor functionality is monitored by the on–board
watchdog circuit. The microprocessor must provide a periodic
low–going signal on the ST input. Should the processor fail to supply
this signal within the selected time–out period (150 msec, 600 msec or
1200 msec), an out–of–control processor is indicated and the
NCP1232 issues a processor reset as a result.
The outputs of the NCP1232 are immediately driven active when
the PB input is brought low by an external push–button switch or other
electronic signal. When connected to a push–button switch, the
NCP1232 provides contact debounce.
The NCP1232 is packaged in a space–saving 8–pin plastic SOIC
package and requires no external components.
Features
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MARKING
DIAGRAM
8
8
1
SO–8
D SUFFIX
CASE 751
1
YY, Y
WW
X
Z
= Year
= Work Week
= Assembly ID Code
= Subcontractor ID Code
NCP
1232
YWWXZ
PIN CONNECTIONS
8–Pin SOIC
NCP1232D
PB RST
TD
TOL
GND
1
2
3
4
8
7
6
5
•
Precision Voltage Monitor
•
•
•
•
•
•
•
•
•
(Adjustable +4.5 V or +4.75 V)
Reset Pulse Width (250 msec Min)
No External Components
Adjustable Watchdog Timer
(150 msec, 600 msec or 1.2 sec)
Debounced Manual Reset Input for External Override
VCC
ST
RST
RST
(Top View)
Applications
ORDERING INFORMATION
Device
NCP1232DR2
Package
SO–8
Shipping
2500 Tape & Reel
Computers
Controllers
Intelligent Instruments
Automotive Systems
Critical
µP
Power Monitoring
©
Semiconductor Components Industries, LLC, 2000
1
May, 2000 – Rev. 0
Publication Order Number:
NCP1232/D
NCP1232
FUNCTIONAL BLOCK DIAGRAM
VD
CC
TOL
5%/10%
TOLERANCE
SELECT
REF
RESET
GENERATOR
RST
RST
PB RST
DEBOUNCE
NCP1232
TD
WATCHDOG
TIMEBASE
SELECT
WATCHDOG
TIMER
ST
GND
PIN DESCRIPTION
Pin No.
(8–Pin SOIC)
1
2
3
4
5
Symbol
PB RST
TD
TOL
GND
RST
Description
Push–button Reset Input. A debounced active–low input that ignores pulses less than 1 msec in
duration and is guaranteed to recognize inputs of 20 msec or greater.
Time Delay Set. The watchdog time–out select input (tTD = 150 msec for
TD = 0 V, tTD = 600 msec for TD = open, tTD = 1.2 sec for TD = VCC.)
Tolerance Input. Connect to GND for 5% tolerance or to VCC for 10% tolerance.
Ground.
Reset Output (Active High) – goes active:
1. If VCC falls below the selected reset voltage threshold
2. If PB RST is forced low
3. If ST is not strobed within the minimum time–out period
4. During power–up
Reset Output (Active Low, Open Drain) – see RST.
Strobe Input. Input for watchdog timer.
The +5 V Power Supply Input.
6
7
8
RST
ST
VCC
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NCP1232
ABSOLUTE MAXIMUM RATINGS*
Voltage on any pin (with respect to GND) –0.3 V to +5.8 V
Rating
Operating Temperature Range
Storage Temperature Range, Tstg
Lead Temperature (Soldering, 10 sec)
Value
–40 to +85
–65 to +150
+300
Unit
°C
°C
°C
*Stresses beyond those listed under “Absolute Maximum Ratings’’ may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(TA = TMIN to TMAX; VCC = +4.5 V to 5.5 V, unless otherwise specified.)
Characteristic
Supply Voltage
ST and PB RST Input High Level
ST and PB RST Input Low Level
Input Leakage ST, TOL
Output Current RST
Current RST, RST
Operating Current
VCC 5% Trip Point (Note 3.)
VCC 10% Trip Point (Note 3.)
Symbol
VCC
VIH
VIL
IL
IOH
IOL
ICC
VCCTP
VCCTP
Test Conditions
–
Note 1.
–
–
VOH = 2.4 V
VOL = 0.4 V
Note 2.
TOL = GND
TOL = VCC
Min
4.5
2.0
–0.3
–1.0
–1.0
2.0
–
4.50
4.25
Typ
5.0
–
–
–
–12
10
50
4.62
4.37
Max
5.5
VCC +0.3
+0.8
+1.0
–
–
200
4.74
4.49
Unit
V
V
V
µA
mA
mA
µA
V
V
CAPACITANCE (Note 4.)
(TA = +25°C)
Characteristic
Input Capacitance ST, TOL
Output Capacitance RST, RST
Symbol
CIN
COUT
Test Conditions
–
–
Min
–
–
Typ
–
–
Max
5.0
7.0
Unit
pF
pF
AC ELECTRICAL CHARACTERISTICS
(TA = TMIN to TMAX; VCC = +5.0 V to
Characteristic
PB RST (Note 5.)
PB RST Delay
Reset Active Time
ST Pulse Width
ST Time–out Period
Symbol
tPB
tPBD
tRST
tST
tTD
Test Conditions
Figure 3
Figure 3
–
Figure 4
Figure 4
TD Pin = 0 V
TD Pin = Open
TD Pin = VCC
Figure 5
Figure 6
"
10%, unless otherwise specified.)
Min
20
1.0
250
20
62.5
250
500
10
0
–
250
Typ
–
4.0
610
–
150
600
1200
–
–
–
610
Max
–
20
1000
–
250
1000
2000
–
–
100
1000
µsec
µsec
nsec
msec
Unit
msec
msec
msec
nsec
msec
VCC Fall Time (Note 4.)
VCC Rise Time (Note 4.)
VCC Detect to RST High and RST Low
VCC Detect to RST High and RST Open
(Note 6.)
1.
2.
3.
4.
5.
6.
tF
tR
tRPD
tRPU
Figure 7, VCC Falling
Figure 8, VCC Rising
PB RST is internally pulled up to VCC with an internal impedance of typically 40 kΩ.
Measured with outputs open.
All voltages references to GND.
Guaranteed by design.
PB RST must be held low for a minimum of 20 msec to guarantee a reset.
tR = 5
µsec.
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NCP1232
Power Monitor
The NCP1232 detects out–of–tolerance power supply
conditions and warns a processor–based system of an
impending power failure. When VCC is detected as below
the preset level defined by TOL, the VCC comparator
outputs the signals RST and RST. If TOL is connected to
ground, the RST and RST signals become active as VCC falls
below 4.75 volts. If TOL is connected to VCC, the RST and
RST become active as VCC falls below 4.5 volts. Because
the processing is stopped at the last possible moment of valid
VCC, the RST and RST are excellent control signals for a
µP.
The reset outputs will remain in their active states until VCC
has been continuously in–tolerance for a minimum of 250
msec allowing the power supply and
µP
to stabilize before
RST is released.
Push–button Reset Input
The debounced manual reset input (PB RST) manually
forces the reset outputs into their active states. Once PB RST
has been low for a time, tPBD, the push–button delay time,
the reset outputs go active. The reset outputs remain in their
active states for a minimum of 250 msec after PB RST rises
above VIH (Figure 3).
A mechanical push–button or active logic signal can drive
the PB RST input. The debounced input ignores input pulses
less than 1 msec and is guaranteed to recognize pulses of
20 msec or greater. No external pull–up resistor is required
because the PB RST input has an internal pull–up to VCC of
approximately 100
µA.
Watchdog Timer
When the ST input is not stimulated for a preset time
period, the watchdog timer function forces RST and RST
signals to the active state. The preset time period is
determined by the TD inputs to be 150 msec with TD
connected to ground, 600 msec with TD open, or 1200 msec
with TD connected to VCC, typical. The watchdog timer
starts timing out from the set time period as soon as RST and
RST are inactive. If a high–to–low transition occurs on the
ST input pin prior to time–out, the watchdog timer is reset
and begins to time–out again. If the watchdog timer is
allowed to time–out, then the RST and RST signals are
driven to the active state for 250 msec minimum (Figure 2).
The software routine that strobes ST is critical. The code
must be in a section of software that is executed regularly so
the time between toggles is less than the watchdog time–out
period. One common technique controls the
µP
I/O line
from two sections of the program. The software might set the
I/O line high while operating in the foreground mode and set
it low while in the background or interrupt mode. If both
modes do not execute correctly, the watchdog timer issues
reset pulses.
Supply Monitor Noise Sensitivity
The NCP1232 is optimized for fast response to
negative–going changes in VDD. Systems with an inordinate
amount of electrical noise on VDD (such as systems using
relays), may require a 0.01
µF
or 0.1
µF
bypass capacitor to
reduce detection sensitivity. This capacitor should be
installed as close to the NCP1232 as possible to keep the
capacitor lead length short.
+5 V
VCC
PB RST
TD
ST
I/O
MICRO–
PROCESSOR
RESET
RST
NCP1232
GND TOL
Figure 1. Push–button Reset
+5 V
10 KΩ
+5 V
3–TERMINAL
REGULATOR
VCC
RST
RESET
MICRO–
PROCESSOR
0.1
µF
NCP1232
ST
TD TOL GND
I/O
Figure 2. Watchdog Timer
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NCP1232
tPB
PB RST
tPBD
VIH
VIL
tRST
RST
RST
Figure 3. Push–button Reset. The debounced PB RST
input ignores input pulses less than 1 msec and is
guaranteed to recognized pulses of 20 msec or greater
PUSH–BUTTON RESET
tST
ST
tTD
Figure 4. Strobe Input
NOTE: tTD is the maximum elapsed time between ST high–to–low
transistions (ST is activated by falling edges only) which will
keep the watchdog timer from forcing the reset outputs active
for a time of tRST. tTD is a function of the voltage at the TD pin,
as tabulated below.
t TD
TYP
150 msec
600 msec
1200 msec
CONDITION
TD PIN = 0 V
TD PIN = OPEN
TD PIN = VCC
MIN
62.5 msec
250 msec
500 msec
MAX
250 msec
1000 msec
2000 msec
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