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NDB4060L

产品描述N-Channel Logic Level Enhancement Mode Field Effect Transistor
产品类别分立半导体    晶体管   
文件大小50KB,共6页
制造商Fairchild
官网地址http://www.fairchildsemi.com/
下载文档 详细参数 全文预览

NDB4060L概述

N-Channel Logic Level Enhancement Mode Field Effect Transistor

NDB4060L规格参数

参数名称属性值
是否Rohs认证不符合
厂商名称Fairchild
包装说明SMALL OUTLINE, R-PSSO-G2
Reach Compliance Codeunknow
ECCN代码EAR99
其他特性LOGIC LEVEL COMPATIBLE
雪崩能效等级(Eas)40 mJ
外壳连接DRAIN
配置SINGLE WITH BUILT-IN DIODE
最小漏源击穿电压60 V
最大漏极电流 (Abs) (ID)15 A
最大漏极电流 (ID)15 A
最大漏源导通电阻0.08 Ω
FET 技术METAL-OXIDE SEMICONDUCTOR
JEDEC-95代码TO-263AB
JESD-30 代码R-PSSO-G2
JESD-609代码e0
元件数量1
端子数量2
工作模式ENHANCEMENT MODE
最高工作温度175 °C
封装主体材料PLASTIC/EPOXY
封装形状RECTANGULAR
封装形式SMALL OUTLINE
峰值回流温度(摄氏度)NOT SPECIFIED
极性/信道类型N-CHANNEL
最大功率耗散 (Abs)50 W
最大脉冲漏极电流 (IDM)45 A
认证状态Not Qualified
表面贴装YES
端子面层Tin/Lead (Sn/Pb)
端子形式GULL WING
端子位置SINGLE
处于峰值回流温度下的最长时间NOT SPECIFIED
晶体管应用SWITCHING
晶体管元件材料SILICON

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April 1996
NDP4060L / NDB4060L
N-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
These logic level N-Channel enhancement mode power
field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This
very high density process has been especially tailored to
minimize on-state resistance, provide superior switching
performance, and withstand high energy pulses in the
avalanche and commutation modes. These devices are
particularly suited for low voltage applications such as
automotive, DC/DC converters, PWM motor controls,
and other battery powered circuits where fast switching,
low in-line power loss, and resistance to transients are
needed.
Features
15A, 60V. R
DS(ON)
= 0.1
@ V
GS
= 5V
Low drive requirements allowing operation directly from logic
drivers. V
GS(TH)
< 2.0V.
Critical DC electrical parameters specified at elevated
temperature.
Rugged internal source-drain diode can eliminate the need
for an external Zener diode transient suppressor.
175°C maximum junction temperature rating.
High density cell design for extremely low R
DS(ON)
.
TO-220 and TO-263 (D
2
PAK) package for both through hole
and surface mount applications.
________________________________________________________________________________
D
G
S
Absolute Maximum Ratings
Symbol
V
DSS
V
DGR
V
GSS
I
D
Parameter
Drain-Source Voltage
T
C
= 25°C unless otherwise noted
NDP4060L
60
60
± 16
± 25
15
45
50
0.33
-65 to 175
275
NDB4060L
Units
V
V
V
Drain-Gate Voltage (R
GS
< 1 M
)
Gate-Source Voltage - Continuous
- Nonrepetitive (t
P
< 50 µs)
Drain Current
- Continuous
- Pulsed
A
P
D
Total Power Dissipation @ T
C
= 25°C
Derate above 25°C
W
W/°C
°C
°C
T
J
,T
STG
T
L
Operating and Storage Temperature
Maximum lead temperature for soldering
purposes, 1/8" from case for 5 seconds
© 1997 Fairchild Semiconductor Corporation
NDP4060L Rev. B / NDB4060L Rev. C

 
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