74HC107; 74HCT107
Dual JK flip-flop with reset; negative-edge trigger
Rev. 5 — 30 November 2015
Product data sheet
1. General description
The 74HC107; 74HCT107 is a dual negative edge triggered JK flip-flop featuring
individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q
outputs. The reset is an asynchronous active LOW input and operates independently of
the clock input. The J and K inputs control the state changes of the flip-flops as described
in the mode select function table. The J and K inputs must be stable one set-up time prior
to the HIGH-to-LOW clock transition for predictable operation. Inputs include clamp
diodes that enable the use of current limiting resistors to interface inputs to voltages in
excess of V
CC
.
2. Features and benefits
Complies with JEDEC standard no. 7A
Input levels:
The 74HC107: CMOS levels
The 74HCT107: TTL levels
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from
40 C
to +85
C
and from
40 C
to +125
C
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74HC107D
74HCT107D
74HC107DB
74HC107PW
40 C
to +125
C
40 C
to +125
C
SSOP14
TSSOP14
40 C
to +125
C
Name
SO14
Description
plastic small outline package; 14 leads; body width
3.9 mm
plastic shrink small outline package; 14 leads; body
width 5.3 mm
Version
SOT108-1
SOT337-1
Type number
plastic thin shrink small outline package; 14 leads; body SOT402-1
width 4.4 mm
Nexperia
74HC107; 74HCT107
Dual JK flip-flop with reset; negative-edge trigger
4. Functional diagram
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
Fig 3.
Logic diagram (one flip-flop)
74HC_HCT107
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 5 — 30 November 2015
2 of 18
Nexperia
74HC107; 74HCT107
Dual JK flip-flop with reset; negative-edge trigger
5. Pinning information
5.1 Pinning
Fig 4.
Pin configuration SO14 and (T)SSOP14
5.2 Pin description
Table 2.
Symbol
1J, 2J
1Q, 2Q
1Q, 2Q
1K, 2K
1CP, 2CP
1R, 2R
GND
V
CC
Pin description
Pin
1, 8
2, 6
3, 5
4, 11
12, 9
13, 10
7
14
Description
synchronous J input
complement output
true output
synchronous K input
clock input (HIGH-to-LOW edge-triggered)
asynchronous reset input (active LOW)
ground (0 V)
supply voltage
74HC_HCT107
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 5 — 30 November 2015
3 of 18
Nexperia
74HC107; 74HCT107
Dual JK flip-flop with reset; negative-edge trigger
6. Functional description
Table 3.
Input
R
L
H
H
H
H
[1]
Function table
[1]
Output
CP
X
J
X
h
l
h
l
K
X
h
h
l
l
Q
L
q
L
H
q
Q
H
q
H
L
q
asynchronous reset
toggle
load 0 (reset)
load 1 (set)
hold (no change)
Operating mode
H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW clock transition;
L = LOW voltage level;
I = LOW voltage level one set-up time prior to the HIGH-to-LOW clock transition;
q = state of referenced output one set-up time prior to the HIGH-to-LOW clock transition;
X = don’t care;
= HIGH-to-LOW clock transition.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
Parameter
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
T
amb
=
40 C
to +125
C
SO14 package
(T)SSOP14 package
[1]
[2]
[3]
[2]
[3]
Conditions
V
I
<
0.5
V or V
I
> V
CC
+ 0.5 V
V
O
<
0.5
V or V
O
> V
CC
+ 0.5 V
V
O
=
0.5
V to V
CC
+ 0.5 V
[1]
[1]
Min
0.5
-
-
-
-
50
65
-
-
Max
+7.0
20
20
25
50
-
+150
500
500
Unit
V
mA
mA
mA
mA
mA
C
mW
mW
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
P
tot
derates linearly with 8 mW/K above 70
C.
P
tot
derates linearly with 5.5 mW/K above 60
C.
74HC_HCT107
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 5 — 30 November 2015
4 of 18
Nexperia
74HC107; 74HCT107
Dual JK flip-flop with reset; negative-edge trigger
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter
V
CC
V
I
V
O
T
amb
t/V
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
Conditions
Min
2.0
0
0
40
-
-
-
74HC107
Typ
5.0
-
-
+25
-
1.67
-
Max
6.0
V
CC
V
CC
+125
625
139
83
Min
4.5
0
0
40
-
-
-
74HCT107
Typ
5.0
-
-
+25
-
1.67
-
Max
5.5
V
CC
V
CC
+125
-
139
-
V
V
V
C
ns/V
ns/V
ns/V
Unit
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
74HC107
V
IH
HIGH-level
input voltage
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
V
IL
LOW-level
input voltage
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
V
OH
HIGH-level
output voltage
V
I
= V
IH
or V
IL
I
O
=
20 A;
V
CC
= 2.0 V
I
O
=
20 A;
V
CC
= 4.5 V
I
O
=
20 A;
V
CC
= 6.0 V
I
O
=
4.0
mA; V
CC
= 4.5 V
I
O
=
5.2
mA; V
CC
= 6.0 V
V
OL
LOW-level
output voltage
V
I
= V
IH
or V
IL
I
O
= 20
A;
V
CC
= 2.0 V
I
O
= 20
A;
V
CC
= 4.5 V
I
O
= 20
A;
V
CC
= 6.0 V
I
O
= 4.0 mA; V
CC
= 4.5 V
I
O
= 5.2 mA; V
CC
= 6.0 V
I
I
I
CC
input leakage
current
supply current
V
I
= V
CC
or GND;
V
CC
= 6.0 V
V
I
= V
CC
or GND; I
O
= 0 A;
V
CC
= 6.0 V
-
-
-
-
-
-
-
0
0
0
0.15
0.16
-
-
0.1
0.1
0.1
0.26
0.26
0.1
4.0
-
-
-
-
-
-
-
0.1
0.1
0.1
0.33
0.33
1.0
40
-
-
-
-
-
-
-
0.1
0.1
0.1
0.4
0.4
1.0
80
V
V
V
V
V
A
A
1.9
4.4
5.9
3.98
5.48
2.0
4.5
6.0
4.32
5.81
-
-
-
-
-
1.9
4.4
5.9
3.84
5.34
-
-
-
-
-
1.9
4.4
5.9
3.7
5.2
-
-
-
-
-
V
V
V
V
V
1.5
3.15
4.2
-
-
-
1.2
2.4
3.2
0.8
2.1
2.8
-
-
-
0.5
1.35
1.8
1.5
3.15
4.2
-
-
-
-
-
-
0.5
1.35
1.8
1.5
3.15
4.2
-
-
-
-
-
-
0.5
1.35
1.8
V
V
V
V
V
V
Conditions
Min
25
C
Typ
Max
40 C
to +85
C 40 C
to +125
C
Unit
Min
Max
Min
Max
74HC_HCT107
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 5 — 30 November 2015
5 of 18
嵌入式系统
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