May 1996
NDH8447
P-Channel Enhancement Mode Field Effect Transistor
General Description
These P-Channel enhancement mode power field effect
transistors are produced using Fairchild's proprietary, high cell
density, DMOS technology. This very high density process is
especially tailored to minimize on-state resistance and provide
superior switching performance. These devices are particularly
suited for low voltage applications such as notebook computer
power management and other battery powered circuits where
fast switching, low in-line power loss, and resistance to
transients are needed.
Features
-4.4A, -30V. R
DS(ON)
= 0.053 @ V
GS
= -10V
R
DS(ON)
= 0.095
Ω
@ V
GS
= -4.5V
High density cell design for extremely low R
DS(ON).
Enhanced SuperSOT
TM
-8 small outline surface mount
package with high power and current handling capability.
____________________________________________________________________________________________
5
6
7
8
4
3
2
1
SuperSOT
TM
-8
Absolute Maximum Ratings
Symbol
V
DSS
V
GSS
I
D
Parameter
Drain-Source Voltage
Gate-Source Voltage
Drain Current - Continuous
- Pulsed
P
D
T
A
= 25°C unless otherwise note
NDH8447
-30
-20
(Note 1a)
Units
V
V
A
-4.4
-20
Maximum Power Dissipation
(Note 1a)
(Note 1b)
(Note 1c)
1.8
1
0.9
-55 to 150
W
T
J
,T
STG
Operating and Storage Temperature Range
°C
THERMAL CHARACTERISTICS
R
θ
JA
R
θ
JC
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Case
(Note 1a)
(Note 1)
70
20
°C/W
°C/W
© 1997 Fairchild Semiconductor Corporation
NDH8447 Rev. C1
Electrical Characteristics
(T
A
= 25°C unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
OFF CHARACTERISTICS
BV
DSS
I
DSS
I
GSSF
I
GSSR
V
GS(th)
R
DS(ON)
Drain-Source Breakdown Voltage
Zero Gate Voltage Drain Current
V
GS
= 0 V, I
D
= -250 µA
V
DS
= -24 V, V
GS
= 0 V
T
J
= 55°C
Gate - Body Leakage, Forward
Gate - Body Leakage, Reverse
V
GS
= 20 V, V
DS
= 0 V
V
GS
= -20 V, V
DS
= 0 V
V
DS
= V
GS
, I
D
= -250 µA
T
J
= 125°C
Static Drain-Source On-Resistance
V
GS
= -10 V, I
D
= -4.4 A
T
J
= 125°C
V
GS
= -4.5 V, I
D
= -3.4 A
I
D(on)
g
FS
C
iss
C
oss
C
rss
t
D(on)
t
r
t
D(off)
t
f
Q
g
Q
gs
Q
gd
On-State Drain Current
Forward Transconductance
V
GS
= -10 V, V
DS
= -5 V
V
DS
= -10 V, I
D
= -4.4 A
V
DS
= -15 V, V
GS
= 0 V,
f = 1.0 MHz
-15
7
-1
-0.7
-1.5
-1.2
0.045
0.075
0.08
-30
-1
-10
100
-100
V
µA
µA
nA
nA
ON CHARACTERISTICS
(Note 2)
Gate Threshold Voltage
-3
-2.2
0.053
0.11
0.095
A
S
V
Ω
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
670
430
160
pF
pF
pF
SWITCHING CHARACTERISTICS
(Note 2)
Turn - On Delay Time
Turn - On Rise Time
Turn - Off Delay Time
Turn - Off Fall Time
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
V
DS
= -15 V,
I
D
= -4.4 A, V
GS
= -10 V
V
DD
= -15 V, I
D
= -1 A,
V
GEN
= -10 V, R
GEN
= 6
Ω
11
15
36
27
20
2.8
6
20
25
50
40
30
ns
ns
ns
ns
nC
nC
nC
NDH8447 Rev. C1
Electrical Characteristics
(T
A
= 25°C unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
-1.5
(Note 2)
Units
A
V
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
V
SD
Notes:
1. R
θ
JA
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
θ
JC
is guaranteed by
design while R
θ
CA
is determined by the user's board design.
Maximum Continuous Drain-Source Diode Forward Current
Drain-Source Diode Forward Voltage
V
GS
= 0 V, I
S
= -1.5 A
-0.8
-1.2
P
D
(
t
) =
R
θ
JA
(
t
)
T
J
−
T
A
=
T
J
−
T
A
R
θ
JC
+
R
θ
C
(
t
)
A
=
I
2
(
t
) ×
R
DS
(
ON
)
D
T
J
Typical R
θ
JA
using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:
a. 70
o
C/W when mounted on a 1 in
2
pad of 2oz cpper.
b. 125
o
C/W when mounted on a 0.026 in
2
pad of 2oz copper.
c. 135
o
C/W when mounted on a 0.005 in
2
pad of 2oz copper.
1a
1b
1c
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
NDH8447 Rev. C1
Typical Electrical Characteristics
-20
3
I
D
, DRAIN-SOURCE CURRENT (A)
-5.0
-15
DRAIN-SOURCE ON-RESISTANCE
V
GS
= -10V
-8.0 -6.0
-4.5
R
DS(on)
, NORMALIZED
V
GS
= -3.5V
2.5
-4.0
-4.5
-5.0
-4.0
-10
2
-3.5
-5
1.5
-6.0
-8.0
-10
-3.0
1
0
0
-1
-2
V
DS
, DRAIN-SOURCE VOLTAGE (V)
-3
0.5
0
-5
-10
I
D
, DRAIN CURRENT (A)
-15
-20
Figure 1. On-Region Characteristics.
Figure 2. On-Resistance Variation
with Drain Current and Gate Voltage.
1.6
2
DRAIN-SOURCE ON-RESISTANCE
1.4
DRAIN-SOURCE ON-RESISTANCE
R
DS(ON)
, NORMALIZED
I
D
=-4.4A
V
GS
= -10V
R
DS(on)
, NORMALIZED
V
GS
= -10V
1.5
1.2
TJ = 125°C
1
25°C
1
0.8
-55°C
0.6
-50
-25
0
25
50
75
100
T , JUNCTION TEMPERATURE (°C)
J
125
150
0.5
0
-5
-10
I
D
, DRAIN CURRENT (A)
-15
-20
Figure 3. On-Resistance Variation
with Temperature
.
Figure 4. On-Resistance Variation
with Drain Current and Temperature
.
-15
1.2
V
DS
= -10V
I
D
, DRAIN CURRENT (A)
-12
25°C
125°C
V
th
, NORMALIZED
GATE-SOURCE THRESHOLD VOLTAGE
T = -55°C
J
V
DS
= V
GS
1.1
I
D
= -250µA
-9
1
-6
0.9
-3
0.8
0
-1
-2
-3
-4
V
GS
, GATE TO SOURCE VOLTAGE (V)
-5
0.7
-50
-25
0
25
50
75
100
T
J
, JUNCTION TEMPERATURE (°C)
125
150
Figure 5. Transfer Characteristics.
Figure 6. Gate Threshold Variation
with Temperature
.
NDH8447 Rev. C1
Typical Electrical Characteristics
(continued)
1.1
20
DRAIN-SOURCE BREAKDOWN VOLTAGE
1.08
1.06
1.04
1.02
1
0.98
0.96
0.94
-50
-I
S
, REVERSE DRAIN CURRENT (A)
I
D
= -250µA
10
5
V
GS
= 0V
BV
DSS
, NORMALIZED
1
0.5
T = 125°C
J
25°C
-55°C
0.1
0.01
-25
0
25
50
75
100
T
J
, JUNCTION TEMPERATURE (°C)
125
150
0.001
0.2
0.4
0.6
0.8
1
-V
SD
, BODY DIODE FORWARD VOLTAGE (V)
1.2
Figure 7. Breakdown Voltage Variation with
Temperature.
Figure 8. Body Diode Forward Voltage Variation
with Source Current and
Temperature.
2000
10
I
D
= -4.4A
-V
GS
, GATE-SOURCE VOLTAGE (V)
1000
CAPACITANCE (pF)
V
DS
= -5.0V
-10V
-15V
C iss
C oss
8
500
300
200
6
C rss
f = 1 MHz
V
GS
= 0V
4
100
2
50
0.1
0.2
0.5
1
2
5
10
-V
DS
, DRAIN TO SOURCE VOLTAGE (V)
30
0
0
4
8
12
Q
g
, GATE CHARGE (nC)
16
20
Figure 9. Capacitance Characteristics.
Figure 10. Gate Charge Characteristics
.
-V
DD
t
d(on)
t
on
t
off
t
r
90%
t
d(off)
90%
V
IN
D
R
L
V
OUT
V
OUT
10%
t
f
V
GS
R
GEN
10%
90%
G
DUT
S
V
IN
10%
50%
50%
PULSE W IDTH
INVERTED
Figure 11. Switching Test Circuit
.
Figure 12. Switching Waveforms
.
NDH8447 Rev. C1
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