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74LVC827A
10-bit buffer/line driver with 5 V tolerant inputs/outputs;
3-state
Rev. 4 — 25 November 2011
Product data sheet
1. General description
The 74LVC827A is a 10-bit buffer/line driver with 3-state outputs. The 3-state outputs are
controlled by the output enable pins OE1 and OE2. A HIGH on pin OEn causes the
outputs to assume a high-impedance OFF-state.
Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be
applied to the outputs. These features allow the use of these devices as translators in
mixed 3.3 V and 5 V applications.
2. Features and benefits
5 V tolerant inputs/outputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
Direct interface with TTL levels
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115B exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Specified from
40 C
to +85
C
and
40 C
to +125
C
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74LVC827AD
74LVC827ADB
74LVC827APW
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
Name
SO24
SSOP24
TSSOP24
Description
plastic small outline package; 24 leads;
body width 7.5 mm
plastic shrink small outline package; 24 leads;
body width 5.3 mm
plastic thin shrink small package outline package;
24 leads; body width 4.4 mm
Version
SOT137-1
SOT340-1
SOT355-1
Type number
NXP Semiconductors
74LVC827A
10-bit buffer/line driver with 5 V tolerant inputs/outputs; 3-state
4. Functional diagram
A0
Y0
2
23
3
A1
Y1
22
4
A2
Y2
21
5
A3
Y3
20
6
A4
Y4
19
7
A5
Y5
18
1
&
13
17
2
23
22
21
20
19
18
17
16
15
14
001aaa617
8
A6
Y6
EN
9
A7
Y7
16
3
4
10
A8
Y8
15
5
6
11
A9
Y9
14
7
8
9
OE1
1
13
OE2
001aaa616
10
11
Fig 1.
Logic diagram
Fig 2.
IEC logic symbol
74LVC827A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 4 — 25 November 2011
2 of 16
NXP Semiconductors
74LVC827A
10-bit buffer/line driver with 5 V tolerant inputs/outputs; 3-state
5. Pinning information
5.1 Pinning
74LVC827A
OE1
A0
A1
A2
A3
A4
A5
A6
A7
1
2
3
4
5
6
7
8
9
24 V
CC
23 Y0
22 Y1
21 Y2
20 Y3
19 Y4
18 Y5
17 Y6
16 Y7
15 Y8
14 Y9
13 OE2
001aaa615
A8 10
A9 11
GND 12
Fig 3.
Pin configuration SO24 and (T)SSOP24
5.2 Pin description
Table 2.
Symbol
OE1
OE2
A[0:9]
Y[0:9]
GND
V
CC
Pin description
Pin
1
13
2, 3, 4, 5, 6, 7, 8, 9, 10, 11
23, 22, 21, 20, 19, 18, 17, 16, 15, 14
12
24
Description
output enable input 1 (active LOW)
output enable input 2 (active LOW)
data input
data output
ground (0 V)
supply voltage
74LVC827A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 4 — 25 November 2011
3 of 16
NXP Semiconductors
74LVC827A
10-bit buffer/line driver with 5 V tolerant inputs/outputs; 3-state
6. Functional description
Table 3.
Control
OE1
L
L
X
H
[1]
H = HIGH voltage level
L = LOW voltage level
X = don’t care
Z = high-impedance OFF-state
Function table
[1]
Input
OE2
L
L
H
X
An
L
H
X
X
Output
Yn
L
H
Z
Z
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
[3]
Parameter
supply voltage
input voltage
output voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
[1]
Min
0.5
0.5
0.5
0.5
50
-
-
-
100
65
Max
+6.5
+6.5
V
CC
+ 0.5
+6.5
-
50
50
100
-
+150
500
Unit
V
V
V
V
mA
mA
mA
mA
mA
C
mW
output HIGH or LOW state
output 3-state
V
I
< 0 V
V
O
> V
CC
or V
O
< 0 V
V
O
= 0 V to V
CC
[2]
[2]
T
amb
=
40 C
to +125
C
[3]
The minimum input voltage ratings may be exceeded if the input current ratings are observed.
The output voltage ratings may be exceeded if the output current ratings are observed.
SO24 package: P
tot
derates linearly with 8 mW/K above 70
C.
(T)SSOP24 package: P
tot
derates linearly with 5.5 mW/K above 60
C.
74LVC827A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 4 — 25 November 2011
4 of 16
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