Freescale Semiconductor
Product Brief
Document Number: K50PB
Rev. 8, 5/2011
Supports all K50, K51, K52, and K53 devices
K50 Family Product Brief
Contents
1 Kinetis Portfolio
Kinetis is the most scalable portfolio of low power, mixed-
signal ARM
®
Cortex
™
-M4 MCUs in the industry. Phase 1 of
the portfolio consists of five MCU families with over 200 pin-,
peripheral- and software-compatible devices. Each family
offers excellent performance, memory and feature scalability
with common peripherals, memory maps, and packages
providing easy migration both within and between families.
Kinetis MCUs are built from Freescale’s innovative 90nm
Thin Film Storage (TFS) flash technology with unique
FlexMemory. Kinetis MCU families combine the latest low-
power innovations and high performance, high precision
mixed-signal capability with a broad range of connectivity,
human-machine interface, and safety & security peripherals.
Kinetis MCUs are supported by a market-leading enablement
bundle from Freescale and numerous ARM 3rd party
ecosystem partners.
1
2
3
4
5
6
7
Kinetis Portfolio................................................................1
K50 Family Introduction...................................................3
K50 Block Diagram..........................................................3
Features.............................................................................5
Power modes...................................................................36
Developer Environment..................................................38
Revision History.............................................................43
© 2010–2011 Freescale Semiconductor, Inc.
Kinetis Portfolio
K70 Family
512KB-1MB
196-256pin
Family
Program
Flash
Packages
100-256pin
64-144pin
64-144pin
64-144pin
32-144pin
32-144pin
Mixed signal
USB
Key Features
K60 Family
256KB-1MB
K50 Family
128-512KB
K40 Family
K30 Family
K20 Family
K10 Family
64-512KB
64-512KB
32KB-1MB
32KB-1MB
Low power
Segment LCD
DDR
Ethernet
Encryption and Tamper Detect
Operational &
transimpedance
amplifiers
Figure 1. Kinetis MCU portfolio
Graphic LCD
All Kinetis families include a powerful array of analog, communication and timing and control peripherals with the level of
feature integration increasing with flash memory size and the number of inputs/outputs. Features common to all Kinetis
families include:
• Core:
• ARM Cortex-M4 Core delivering 1.25 DMIPS/MHz with DSP instructions (floating-point unit available on
certain Kinetis families)
• Up to 32-channel DMA for peripheral and memory servicing with minimal CPU intervention
• Broad range of performance levels rated at maximum CPU frequencies of 50 MHz, 72 MHz, 100 MHz, 120
MHz, and 150 MHz
• Ultra-low power:
• 10 low power operating modes for optimizing peripheral activity and wake-up times for extended battery life.
• Low–leakage wake-up unit, low power timer, and low power RTC for additional low power flexibility
• Industry-leading fast wake-up times
• Memory:
• Scalable memory footprints from 32 KB flash / 8 KB RAM to 1 MB flash / 128 KB RAM. Independent flash
banks enable concurrent code execution and firmware updates
• Optional 16 KB cache memory for optimizing bus bandwidth and flash execution performance. Offered on K10,
K20, and K60 family devices with CPU performance of up to 150 MHz.
• FlexMemory with up to 512 KB FlexNVM and up to 16 KB FlexRAM. FlexNVM can be partitioned to support
additional program flash memory (ex. bootloader), data flash (ex. storage for large tables), or EEPROM backup.
FlexRAM supports EEPROM byte-write/byte-erase operations and dictates the maximum EEPROM size.
• EEPROM endurance capable of exceeding 10 million cycles
K50 Family Product Brief, Rev. 8, 5/2011
2
Freescale Semiconductor, Inc.
K50 Family Introduction
• EEPROM erase/write times an order of magnitude faster than traditional EEPROM
• Multi-function external bus interface capable of interfacing to external memories, gate-array logic, or an LCD
• Mixed-signal analog:
• Fast, high precision 16-bit ADCs, 12-bit DACs, programmable gain amplifiers, high speed comparators and an
internal voltage reference. Powerful signal conditioning, conversion and analysis capability with reduced system
cost
• Human Machine Interface (HMI):
• Capacitive Touch Sensing Interface with full low-power support and minimal current adder when enabled
• Connectivity and Communications:
• UARTs with ISO7816 and IrDA support, I2S, CAN, I2C and DSPI
• USB OTG controller
• Reliability, Safety and Security:
• Hardware cyclic redundancy check engine for validating memory contents/communication data and increased
system reliability
• Independent-clocked COP for protection against code runaway in fail-safe applications
• External watchdog monitor
• Timing and Control:
• Powerful FlexTimers which support general purpose, PWM, and motor control functions
• Carrier Modulator Transmitter for IR waveform generation
• Programmable Interrupt Timer for RTOS task scheduler time base or trigger source for ADC conversion and
programmable delay block
• System:
• 5 V tolerant GPIO with pin interrupt functionality
• Wide operating voltage range from 1.71 V to 3.6 V with flash programmable down to 1.71 V with fully
functional flash and analog peripherals
• Ambient operating temperature ranges from -40 °C to 105 °C
2 K50 Family Introduction
The K50 MCU family includes a flexible, low-power segment LCD controller with support for up to 320 segments, analog
front end capability, and full-speed USB 2.0 On-The-Go with device charger detect capability. Devices start from 128 KB of
flash in 64QFN packages extending up to 512 KB in a 144MAPBGA package with a rich suite of analog, communication,
timing and control peripherals. High-memory desnsity K50 family devices include IEEE1588 Ethernet.
3 K50 Block Diagram
The below figure shows a superset block diagram of the K50 device. Other devices within the family have a subset of the
features.
K50 Family Product Brief, Rev. 8, 5/2011
Freescale Semiconductor, Inc.
3
K50 Block Diagram
Kinetis K50 Family
ARM
®
Cortex™-M4
Core
System
Internal
and external
watchdogs
Debug
interfaces
Interrupt
controller
DSP
Memory
protection
Memories and Memory Interfaces
Program
flash
Clocks
Phase-
locked loop
Frequency-
locked loop
RAM
FlexMemory
Serial
programming
interface
DMA
External
bus
Low/high
frequency
oscillators
Internal
reference
clocks
Low-leakage
wakeup
and Integrity
CRC
Random
number
generator
Hardware
encryption
Security
Analog
16-bit ADC
x2
PGA
x2
Analog
comparator
x3
6-bit DAC
x3
12-bit DAC
x2
Voltage
reference
Op-amp
x2
Trans-
impedance
amplifier
x2
Timers
Timers
x3 (12ch)
Carrier
modulator
transmitter
Programmable
Communication Interfaces
I C
x2
UART
x6
SPI
x3
2
Human-Machine
Interface (HMI)
GPIO
Xtrinsic
touch-sensing
interface
Segment
LCD
I S
2
Secure
Digital
USB OTG
LS/FS
USB LS/FS
transceiver
delay block
Periodic
interrupt
timers
Low power
timer
IEEE 1588
Ethernet
USB charger
detect
USB voltage
regulator
Independent
real-time
clock
IEEE 1588
Timers
LEGEND
Migration difference from K60 family
Figure 2. K50 Block Diagram
K50 Family Product Brief, Rev. 8, 5/2011
4
Freescale Semiconductor, Inc.
Features
4 Features
4.1 Common features among the K50 family
All devices within the K50 family features the following at a minimum:
Table 1. Common features among all K50 devices
Operating characteristics
•
•
•
•
•
•
•
•
•
Voltage range 1.71V - 3.6V
Flash memory programming down to 1.71V
Temperature range (T
A
) -40 to 85°C
Flexible modes of operation
Next generation 32-bit ARM Cortex-M4 core
Supports DSP instructions
Nested vectored interrupt controller (NVIC)
Asynchronous wake-up interrupt controller (AWIC)
Debug & trace capability
• 2-pin serial wire debug (SWD)
• IEEE 1149.1 Joint Test Action Group (JTAG)
• IEEE 1149.7 compact JTAG (cJTAG)
• Trace port interface unit (TPIU)
• Flash patch and breakpoint (FPB)
• Data watchpoint and trace (DWT)
• Instrumentation trace macrocell (ITM)
Core features
System and power management
• Software and hardware watchdog with external monitor
pin
• DMA controller
• Low-leakage wake-up unit (LLWU)
• Power management controller with 10 different power
modes
• Non-maskable interrupt (NMI)
• 128-bit unique identification (ID) number per chip
• Multi-purpose clock generator
• PLL and FLL operation
• Internal reference clocks
•
•
•
•
3MHz to 32MHz crystal oscillator
32kHz to 40kHz crystal oscillator
Internal 1kHz low power oscillator
DC to 50MHz external square wave input clock
Clocks
Memories and Memory Interfaces
• FlexMemory consisting of FlexNVM (non-volatile flash
memory that can execute program code, store data, or
backup EEPROM data) or FlexRAM (RAM memory
that can be used as traditional RAM or as high-
endurance EEPROM storage, and also accelerates
flash programming)
• Flash security and protection features
• Serial flash programming interface (EzPort)
• Cyclic redundancy check (CRC)
Table continues on the next page...
Security and integrity
K50 Family Product Brief, Rev. 8, 5/2011
Freescale Semiconductor, Inc.
5
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