April 1997
NDS351AN
N-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
These N-Channel logic level enhancement mode power field
effect transistors are produced using Fairchild's proprietary,
high cell density, DMOS technology. This very high density
process is especially tailored to minimize on-state resistance.
These devices are particularly suited for low voltage
applications in notebook computers, portable phones, PCMCIA
cards, and
other battery powered circuits where fast
switching, and low in-line power loss are needed in a very small
outline surface mount package.
Features
1.2A, 30 V. R
DS(ON)
= 0.25
Ω
@ V
GS
= 4.5 V
R
DS(ON)
= 0.16
Ω
@ V
GS
= 10 V.
Industry standard outline SOT-23 surface mount package
using proprietary SuperSOT
TM
-3 design for superior
thermal and electrical capabilities.
High density cell design for extremely low R
DS(ON)
.
Exceptional on-resistance and maximum DC current
capability.
Compact industry standard SOT-23 surface mount
_________________________________________________________________________________
D
G
S
Absolute Maximum Ratings
Symbol
V
DSS
V
GSS
I
D
P
D
T
J
,T
STG
Parameter
Drain-Source Voltage
T
A
= 25°C unless otherwise noted
NDS351AN
30
20
(Note 1a)
Units
V
V
A
Gate-Source Voltage - Continuous
Maximum Drain Current - Continuous
- Pulsed
Maximum Power Dissipation
(Note 1a)
(Note 1b)
± 1.2
± 10
0.5
0.46
-55 to 150
W
Operating and Storage Temperature Range
°C
THERMAL CHARACTERISTICS
R
θ
JA
R
θ
JC
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Case
(Note 1a)
(Note 1)
250
75
°C/W
°C/W
© 1997 Fairchild Semiconductor Corporation
NDS351AN Rev. C
Electrical Characteristics
(T
A
= 25°C unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
OFF CHARACTERISTICS
BV
DSS
I
DSS
I
GSSF
I
GSSR
V
GS(th)
R
DS(ON)
Drain-Source Breakdown Voltage
Zero Gate Voltage Drain Current
V
GS
= 0 V, I
D
= 250 µA
V
DS
= 24 V, V
GS
= 0 V
T
J
=125°C
Gate - Body Leakage, Forward
Gate - Body Leakage, Reverse
V
GS
= 20 V
DS
= 0 V
V
GS
= -20 V, V
DS
= 0 V
V
DS
= V
GS
, I
D
= 250 µA
T
J
=125°C
Static Drain-Source On-Resistance
V
GS
= 4.5 V, I
D
= 1.2 A
T
J
=125°C
V
GS
= 10 V, I
D
= 1.4 A
I
D(ON)
g
FS
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
Q
g
Q
gs
Q
gd
On-State Drain Current
Forward Transconductance
V
GS
= 4.5 V, V
DS
= 5 V
V
DS
= 5 V, I
D
= 1.2 A,
V
DS
= 10 V, V
GS
= 0 V,
f = 1.0 MHz
3.5
1.8
0.8
0.5
1.7
1.3
0.19
0.28
0.125
30
1
10
100
-100
V
µA
µA
nA
nA
ON CHARACTERISTICS
(Note 2)
Gate Threshold Voltage
2
1.5
0.25
0.37
0.16
A
S
V
Ω
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
(Note 2)
125
100
90
pF
pF
pF
SWITCHING CHARACTERISTICS
Turn - On Delay Time
Turn - On Rise Time
Turn - Off Delay Time
Turn - Off Fall Time
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
V
DD
= 10 V, I
D
= 1 A,
V
GS
= 10 V, R
GEN
= 50
Ω
6
15
14
18
15
30
30
40
2.7
ns
ns
ns
ns
nC
nC
nC
V
DS
= 10 V, I
D
= 1.2 A,
V
GS
= 4.5 V
1.9
0.5
0.9
NDS351AN Rev. C
Electrical Characteristics
(T
A
= 25°C unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
I
SM
V
SD
Notes:
1. R
θ
JA
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of
guaranteed by design while R
θ
CA
is determined by the user's board design.
the drain pins. R
θ
JC
is
Maximum Continuous Drain-Source Diode Forward Current
Maximum Pulsed Drain-Source Diode Forward Current
Drain-Source Diode Forward Voltage
V
GS
= 0 V, I
S
= 1.2 A
(Note 2)
0.8
0.42
5
1.2
A
A
V
P
D
(
t
) =
R
θ
JA
(
t
)
T
J
−
T
A
=
T
J
−
T
A
R
θ
JC
+
R
θ
CA
(
t
)
=
I
2
(
t
) ×
R
DS
(
ON
)
D
T
J
Typical R
θ
JA
using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:
a. 250
o
C/W when mounted on a 0.02 in
2
pad of 2oz copper.
b. 270
o
C/W when mounted on a 0.001 in
2
pad of 2oz copper.
1a
1b
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
NDS351AN Rev. C
Typical Electrical Characteristics
5
1.8
V
GS
=10V
I
D
, DRAIN-SOURCE CURRENT (A)
4
6.0
R
DS(on
)
, NORMALIZED
DRAIN-SOURCE ON-RESISTANCE
5.0
4.5
4.0
1.6
1.4
1.2
1
0.8
0.6
0.4
V
GS
= 3.5V
3
3.5
2
4.0
4.5
5.0
6.0
7.0
10
3.0
1
0
0
V
DS
1
2
3
0
1
, DRAIN-SOURCE VOLTAGE (V)
2
I
D
, DRAIN CURRENT (A)
3
4
Figure 1. On-Region Characteristics
.
Figure 2. On-Resistance Variation
with Drain Current and Gate Voltage
.
1.8
1.8
DRAIN-SOURCE ON-RESISTANCE
I
D
= 1.2A
1.6
1.4
1.2
1
0.8
0.6
0.4
DRAIN-SOURCE ON-RESISTANCE
1.6
V
GS
= 4.5 V
R
DS(ON)
, NORMALIZED
V
GS
= 4.5V
TJ = 125°C
1.4
R
DS(on)
, NORMALIZED
1.2
25°C
-55°C
1
0.8
0.6
-50
-25
0
25
50
75
100
T , JUNCTION TEMPERATURE (°C)
J
125
150
0
1
2
I
D
, DRAIN CURRENT (A)
3
4
Figure 3. On-Resistance Variation
with Temperature
.
Figure 4. On-Resistance Variation
with Drain Current and Temperature
.
5
V
DS
= 5.0V
4
25°C
V
th
, NORMALIZED
GATE-SOURCE THRESHOLD VOLTAGE
T = -55°C
J
1.2
1.1
1
0.9
0.8
0.7
0.6
-50
I
D
, DRAIN CURRENT (A)
125°C
3
V
DS
= V
GS
I
D
= 250µA
2
1
0
0.5
1
1.5
V
GS
2
2.5
3
3.5
4
4.5
5
-25
, GATE TO SOURCE VOLTAGE (V)
0
25
50
75
100
T
J
, JUNCTION TEMPERATURE (°C)
125
150
Figure 5. Transfer Characteristics.
Figure 6. Gate Threshold Variation
with Temperature
.
NDS351AN Rev. C
Typical Electrical Characteristics
(continued)
1.12
5
DRAIN-SOURCE BREAKDOWN VOLTAGE
I , REVERSE DRAIN CURRENT (A)
I
D
= 250µA
1.08
V
GS
= 0V
1
BV
DSS
, NORMALIZED
TJ = 125°C
0.1
25°C
-55°C
1.04
1
0.01
0.96
0.001
0.92
-50
S
-25
0
T
J
25
50
75
100
125
150
0.0001
0
0.2
0.4
0.6
0.8
1
V
SD
, BODY DIODE FORWARD VOLTAGE (V)
1.2
, JUNCTION TEMPERATURE (°C)
Figure 7. Breakdown Voltage Variation with
Temperature
.
Figure 8. Body Diode Forward Voltage Variation with
Source Current and Temperature
.
400
, GATE-SOURCE VOLTAGE (V)
300
CAPACITANCE (pF)
10
I
D
= 1.2A
8
V
DS
= 5V
10V
15V
200
150
6
C iss
100
80
4
C oss
f = 1 MHz
V
GS
= 0V
C rss
50
0.1
V
0.2
V
0.5
DS
GS
2
1
2
5
10
20
30
0
0
1
, DRAIN TO SOURCE VOLTAGE (V)
2
Q
g
, GATE CHARGE (nC)
3
4
Figure 9. Capacitance Characteristics
.
Figure 10. Gate Charge Characteristics
.
V
DD
t
d(on)
t
on
t
off
t
r
90%
t
d(off)
90%
t
f
V
IN
D
R
L
V
OUT
V
OUT
10%
V
GS
R
GEN
10%
INVERTED
G
DUT
90%
S
V
IN
10%
50%
50%
PULSE WIDTH
Figure 11. Switching Test Circuit
.
Figure 12. Switching Waveforms
.
NDS351AN Rev. C
微控制器 MCU
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
