SE98A
DDR memory module temp sensor, 1.7 V to 3.6 V
Rev. 04 — 25 November 2009
Product data sheet
1. General description
The NXP Semiconductors SE98A measures temperature from
−40 °C
and +125
°C
with
JEDEC Grade B
±1 °C
accuracy between +75
°C
and +95
°C
communicating via the
I
2
C-bus/SMBus. It is typically mounted on a Dual In-Line Memory Module (DIMM)
measuring the DRAM temperature in accordance with the new JEDEC (JC-42.4)
Mobile
Platform Memory Module Thermal Sensor Component
specification.
The SE98A thermal sensor operates over the V
DD
range of 1.7 V to 3.6 V. The SE98A
does not include the 2 k SPD and is designed for custom DIMM where larger SPD is
required.
The Temp Sensor (TS) consists of an Analog-to-Digital Converter (ADC) that monitors
and updates its own temperature readings 8 times per second, converts the reading to a
digital data, and latches them into the data temperature registers. User-programmable
registers, such as Shutdown or Low-power modes and the specification of temperature
event and critical output boundaries, provide flexibility for DIMM temperature-sensing
applications.
When the temperature changes beyond the specified boundary limits, the SE98A outputs
an EVENT signal using an open-drain output that can be pulled up between 0.9 V and
3.6 V. The user has the option of setting the EVENT output signal polarity as either an
active LOW or active HIGH comparator output for thermostat operation, or as a
temperature event interrupt output for microprocessor-based systems. The EVENT output
can even be configured as a critical temperature output.
The SE98A supports the industry-standard 2-wire I
2
C-bus/SMBus serial interface. The
SMBus TIMEOUT function is supported to prevent system lock-ups. Manufacturer and
Device ID registers provide the ability to confirm the identify of the device. Three address
pins allow up to eight devices to be controlled on a single bus.
The SE98A is an improved SE98 and is comparable to the thermal sensor in the SE97 but
with voltage range of 1.7 V to 3.6 V.
2. Features
JEDEC (JC-42.4) TS3000B1 DIMM
±
0.5
°C
(typ.) between 75
°C
and 95
°C
temperature sensor
Optimized for voltage range: 1.7 V to 3.6 V
Shutdown current: 0.1
μA
(typ.) and 5.0
μA
(max.)
2-wire interface: I
2
C-bus/SMBus compatible, 0 Hz to 400 kHz
SMBus ALERT and TIMEOUT (programmable)
11-bit ADC Temperature-to-Digital converter with 0.125
°C
resolution
NXP Semiconductors
SE98A
DDR memory module temp sensor, 1.7 V to 3.6 V
Operating current: 250
μA
(typ.) and 400
μA
(max.)
Programmable hysteresis threshold: 0
°C,
1.5
°C,
3
°C,
6
°C
Over/under/critical temperature EVENT output
B grade accuracy:
±0.5 °C/±1 °C
(typ./max.)
→
+75
°C
to +95
°C
±1 °C/±2 °C
(typ./max.)
→
+40
°C
to +125
°C
±2 °C/±3 °C
(typ./max.)
→ −40 °C
to +125
°C
ESD protection exceeds 2000 V HBM per JESD22-A114, 250 V MM per
JESD22-A115, and 1000 V CDM per JESD22-C101
Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
Available packages: TSSOP8, HWSON8 (PSON8 VCED-3) and HXSON8
3. Applications
DDR2 and DDR3 memory modules
Laptops, personal computers and servers
Enterprise networking
Hard disk drives and other PC peripherals
4. Ordering information
Table 1.
Ordering information
Topside
mark
S98A
98A
8AL
Package
Name
TSSOP8
HWSON8
HXSON8
Description
plastic thin shrink small outline package; 8 leads;
body width 4.4 mm
plastic thermal enhanced very very thin small outline package;
no leads; 8 terminals; body 2
×
3
×
0.8 mm
plastic thermal enhanced extremely thin small outline package;
no leads; 8 terminals; body 2
×
3
×
0.5 mm
Version
SOT530-1
SOT1069-2
SOT1052-1
Type number
SE98APW
SE98ATP
[1]
SE98ATL
[1]
Industry standard 2 mm
×
3 mm
×
0.8 mm package to JEDEC VCED-3 PSON8 in 8 mm
×
4 mm pitch tape 4 k quantity reels.
SE98A_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 25 November 2009
2 of 43
NXP Semiconductors
SE98A
DDR memory module temp sensor, 1.7 V to 3.6 V
5. Block diagram
SE98A
TEMPERATURE REGISTER
CRITICAL ALARM TRIP
UPPER ALARM TRIP
LOWER ALARM TRIP
CAPABILITY
MANUFACTURING ID
DEVICE/REV ID
SMBus TIMEOUT/ALERT
CONFIGURATION
•
•
•
•
•
•
•
HYSTERESIS
SHUT DOWN TEMP SENSOR
LOCK PROTECTION
EVENT OUTPUT ON/OFF
EVENT OUTPUT POLARITY
EVENT OUTPUT STATUS
CLEAR EVENT OUTPUT STATUS
10 V
OVERVOLTAGE
R
30 kΩ to 800 kΩ
POR
BAND GAP
TEMPERATURE
SENSOR
V
DD
V
SS
11-BIT
ΔΣ
ADC
EVENT
SMBus/I
2
C-BUS
INTERFACE
FILTER
SCL
SDA
A0
A1
R
30 kΩ to 800 kΩ
A2
POINTER REGISTER
R
30 kΩ to 800 kΩ
002aad756
Fig 1.
Block diagram of SE98A
SE98A_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 25 November 2009
3 of 43
NXP Semiconductors
SE98A
DDR memory module temp sensor, 1.7 V to 3.6 V
6. Pinning information
6.1 Pinning
terminal 1
index area
A0
A1
A0
A1
A2
V
SS
1
2
3
4
002aad757
1
2
8
7
V
DD
EVENT
SCL
SDA
8
V
DD
EVENT
SCL
SDA
SE98ATP
A2
V
SS
3
4
6
5
SE98APW
7
6
5
002aaf008
Transparent top view
Fig 2.
Pin configuration for TSSOP8
terminal 1
index area
A0
A1
A2
V
SS
1
2
3
4
Fig 3.
SE98ATL
Pin configuration for HWSON8
8
7
6
5
V
DD
EVENT
SCL
SDA
002aad910
Transparent top view
Fig 4.
Pin configuration for HXSON8
6.2 Pin description
Table 2.
Symbol
A0
[1]
A1
A2
V
SS
SDA
SCL
EVENT
V
DD
[1]
Pin description
Pin
1
2
3
4
5
6
7
8
Type
I
I
I
ground
I/O
I
O
power
Description
I
2
C-bus/SMBus slave address bit 0 with internal pull-down
I
2
C-bus/SMBus slave address bit 1 with internal pull-down
I
2
C-bus/SMBus slave address bit 2 with internal pull-down
device ground
SMBus/I
2
C-bus serial data input/output (open-drain).
Must have external pull-up resistor.
SMBus/I
2
C-bus serial clock input/output (open-drain).
Must have external pull-up resistor.
Thermal alarm output for high/low and critical temperature
limit (open-drain). Must have external pull-up resistor.
device power supply (1.7 V to 3.6 V)
This input is overvoltage tolerant to support software write protection when applied to SPD.
SE98A_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 25 November 2009
4 of 43
NXP Semiconductors
SE98A
DDR memory module temp sensor, 1.7 V to 3.6 V
7. Functional description
7.1 Serial bus interface
The SE98A uses the 2-wire serial bus (I
2
C-bus/SMBus) to communicate with a host
controller. The serial bus consists of a clock (SCL) and data (SDA) signals. The device
can operate on either the I
2
C-bus Standard/Fast mode or SMBus. The I
2
C-bus
Standard-mode is defined to have bus speeds from 0 Hz to 100 kHz, I
2
C-bus Fast-mode
from 0 Hz to 400 kHz, and the SMBus is from 10 kHz to 100 kHz. The host or bus master
generates the SCL signal, and the SE98A uses the SCL signal to receive or send data on
the SDA line. Data transfer is serial, bidirectional, and is one bit at a time with the Most
Significant Bit (MSB) transferred first, and a complete I
2
C-bus data is 1 byte. Since SCL
and SDA are open-drain, pull-up resistors must be installed on these pins.
7.2 Slave address
The SE98A uses a 4-bit fixed and 3-bit programmable (A0, A1 and A2) 7-bit slave address
that allows a total of eight devices to coexist on the same bus. The input of each pin is
sampled at the start of each I
2
C-bus/SMBus access. The A0, A1 and A2 pins are pulled
LOW internally. The A0 pin is also overvoltage tolerant, supporting 10 V software write
protection when applied to the SPD that shares common address lines.
slave address
MSB
0
0
1
1
A2
A1
LSB
A0
R/W
X
fixed
hardware
selectable
002aab304
Fig 5.
Slave address
SE98A_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 25 November 2009
5 of 43
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