July 1996
NDS8926
Dual N-Channel Enhancement Mode Field Effect Transistor
General Description
These N-Channel enhancement mode power field effect
transistors are produced using Fairchild's proprietary, high cell
density, DMOS technology. This very high density process is
especially tailored to minimize on-state resistance and provide
superior switching performance. These devices are particularly
suited for low voltage applications such as DC motor control
and DC/DC conversion where fast switching, low in-line power
loss, and resistance to transients are needed.
Features
5.5 A, 20 V. R
DS(ON)
= 0.035
Ω
@ V
GS
= 4.5 V
R
DS(ON)
= 0.045
Ω
@ V
GS
= 2.7 V.
High density cell design for extremely low R
DS(ON)
.
High power and current handling capability in a widely used
surface mount package.
Dual MOSFET in surface mount package.
___________________________________________________________________________________________
5
4
3
2
1
6
7
8
Absolute Maximum Ratings
T
A
= 25°C unless otherwise note
Symbol
V
DSS
V
GSS
I
D
P
D
Parameter
Drain-Source Voltage
Gate-Source Voltage
Drain Current - Continuous
- Pulsed
Power Dissipation for Dual Operation
Power Dissipation for Single Operation
(Note 1a)
(Note1b)
(Note1c)
(Note 1a)
NDS8926
20
8
5.5
20
2
1.6
1
0.9
-55 to 150
Units
V
V
A
W
T
J
,T
STG
Operating and Storage Temperature Range
°C
THERMAL CHARACTERISTICS
R
θ
JA
R
θ
JC
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Case
(Note 1a)
78
40
°C/W
°C/W
(Note 1)
© 1997 Fairchild Semiconductor Corporation
NDS8926 Rev. D2
ELECTRICAL CHARACTERISTICS
(T
A
= 25°C unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
OFF CHARACTERISTICS
BV
DSS
I
DSS
I
GSSF
I
GSSR
V
GS(th)
R
DS(ON)
Drain-Source Breakdown Voltage
Zero Gate Voltage Drain Current
Gate - Body Leakage, Forward
Gate - Body Leakage, Reverse
Gate Threshold Voltage
Static Drain-Source On-Resistance
V
GS
= 0 V, I
D
= 250 µA
V
DS
= 16 V, V
GS
= 0 V
T
J
= 55
o
C
V
GS
= 8 V, V
DS
= 0 V
V
GS
= -8 V, V
DS
= 0 V
V
DS
= V
GS
, I
D
= 250 µA
T
J
= 125 C
V
GS
= 4.5 V, I
D
= 5.5 A
T
J
= 125 C
V
GS
= 2.7 V, I
D
= 5 A
I
D(on)
g
FS
C
iss
C
oss
C
rss
t
D(on)
t
r
t
D(off)
t
f
Q
g
Q
gs
Q
gd
On-State Drain Current
Forward Transconductance
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn - On Delay Time
Turn - On Rise Time
Turn - Off Delay Time
Turn - Off Fall Time
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
V
DS
= 10 V,
I
D
= 5.5 A, V
GS
= 4.5 V
V
DD
= 6 V, I
D
= 1 A,
V
GS
= 4.5 V, R
GEN
= 6
Ω
V
GS
= 4.5 V, V
DS
= 5 V
V
GS
= 2.7 V, V
DS
= 5 V
V
DS
= 10 V, I
D
= 5.5 A
V
DS
= 10 V, V
GS
= 0 V,
f = 1.0 MHz
DYNAMIC CHARACTERISTICS
760
440
160
10
30
55
20
21
2.3
6.8
20
50
80
40
30
pF
pF
pF
ns
ns
ns
ns
nC
nC
nC
20
10
14
S
o
o
20
1
10
100
-100
0.4
0.3
0.6
0.35
0.029
0.04
0.035
1
0.8
0.035
0.063
0.045
V
µA
µA
nA
nA
V
ON CHARACTERISTICS
(Note 2)
Ω
A
SWITCHING CHARACTERISTICS
(Note 2)
NDS8926 Rev. D2
ELECTRICAL CHARACTERISTICS
(T
A
= 25°C unless otherwise noted)
Symbol
I
S
V
SD
Notes:
1. R
θ
JA
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
θ
JC
is guaranteed by
design while R
θ
CA
is determined by the user's board design.
Parameter
Conditions
Min
Typ
Max
1.3
Units
A
V
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
Maximum Continuous Drain-Source Diode Forward Current
Drain-Source Diode Forward Voltage
V
GS
= 0 V, I
S
= 1.3 A
(Note 2)
0.8
1.2
P
D
(
t
) =
R
θ
J A
t
)
(
T
J
−
T
A
=
R
θ
J C
R
θ
CA
t
)
+
(
T
J
−
T
A
=
I
2
(
t
) ×
R
DS
(
ON
)
D
T
J
Typical R
θ
JA
for single device operation using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:
a. 78
o
C/W when mounted on a 0.5 in
2
pad of 2oz copper.
b. 125
o
C/W when mounted on a 0.02 in
2
pad of 2oz copper.
c. 135
o
C/W when mounted on a 0.003 in
2
pad of 2oz copper.
1a
1b
1c
Scale 1 : 1 on letter size paper.
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
NDS8926 Rev. D2
Typical Electrical Characteristics
30
I
D
, DRAIN-SOURCE CURRENT (A)
25
20
15
10
5
0
DRAIN-SOURCE ON-RESISTANCE
V
GS
=4.5V
3.5
3.0
2.7
2.5
R
DS(on)
, NORMALIZED
2
1.8
1.6
2.0
V
GS
= 2.0V
1.4
2.5
1.2
1
0.8
2.7
3.0
1.5
3.5
4.5
0
0.5
V
DS
1
1.5
2
, DRAIN-SOURCE VOLTAGE (V)
2.5
3
0
5
10
15
20
25
30
I
D
, DRAIN CURRENT (A)
Figure 1. On-Region Characteristics.
Figure 2. On-Resistance Variation with Gate
Voltage and Drain Current.
1.6
2
DRAIN-SOURCE ON-RESISTANCE
1.4
R
DS(ON)
NORMALIZED
,
V
GS
= 4.5V
R
DS(on)
, NORMALIZED
DRAIN-SOURCE ON-RESISTANCE
I
D
= 5.5A
V
GS
= 4.5 V
TJ = 125°C
1.5
1.2
1
25°C
1
-55°C
0.8
0.6
-50
0.5
-25
0
25
50
75
100
125
150
T
J
, JUNCTION TEMPERATURE (°C)
0
5
10
15
20
I , DRAIN CURRENT (A)
D
25
30
Figure 3. On-Resistance Variation with
Temperature.
Figure 4. On-Resistance Variation with Drain
Current and Temperature.
30
1.4
GATE-SOURCE THRESHOLD VOLTAGE
V
DS
= 5.0V
25
I
D
, DRAIN CURRENT (A)
20
15
10
5
0
T = -55°C
J
25°C
125°C
V
th
, NORMALIZED
1.2
V
DS
= V
GS
I
D
= 250µA
1
0.8
0.6
0
0.5
1.5
2
2.5
3
V
GS
, GATE TO SOURCE VOLTAGE (V)
1
3.5
4
0.4
-50
-25
0
25
50
75
100
T
J
, JUNCTION TEMPERATURE (°C)
125
150
Figure 5. Transfer Characteristics.
Figure 6. Gate Threshold Variation with
Temperature.
NDS8926 Rev. D2
Typical Electrical Characteristics
DRAIN-SOURCE BREAKDOWN VOLTAGE
1.12
I
D
= 250µA
30
10
5
I
S
, REVERSE DRAIN CURRENT (A)
1
V
GS
= 0V
BV
DSS
, NORMALIZED
1.08
TJ = 125°C
0.1
1.04
25°C
-55°C
1
0.01
0.96
0.001
0.92
-50
-25
0
25
50
75
100
T
J
, JUNCTION TEMPERATURE (°C)
125
150
0.0001
0
0.2
0.4
0.6
0.8
1
1.2
V
SD
, BODY DIODE FORWARD VOLTAGE (V)
1.4
Figure 7. Breakdown Voltage Variation with
Temperature.
Figure 8. Body Diode Forward Voltage Variation
with Current and Temperature
.
3000
2000
5
V
GS
, GATE-SOURCE VOLTAGE (V)
I
D
= 5.5A
4
V
DS
= 5V
15V
10V
CAPACITANCE (pF)
1000
C iss
C oss
3
500
300
200
2
f = 1 MHz
V
GS
= 0 V
C rss
1
100
0.1
0
0.2
0.5
1
2
5
10
20
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
0
5
10
15
20
25
Q
g
, GATE CHARGE (nC)
Figure 9. Capacitance Characteristics.
Figure 10. Gate Charge Characteristics.
V
DD
V
IN
D
t
on
t
off
t
r
90%
R
L
V
OUT
DUT
t
d(on)
t
d(off)
90%
t
f
V
GS
V
OUT
R
GEN
10%
10%
INVERTED
G
90%
S
V
IN
10%
50%
50%
PULSE WIDTH
Figure 11. Switching Test Circuit
.
Figure 12. Switching Waveforms
.
NDS8926 Rev. D2
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