19-3542; Rev 0; 2/05
KIT
ATION
EVALU
BLE
AVAILA
16-Bit, 600Msps, High-Dynamic-Performance
DAC with LVDS Inputs
General Description
The MAX5891 advanced 16-bit, 600Msps, digital-to-
analog converter (DAC) meets the demanding perfor-
mance requirements of signal synthesis applications
found in wireless base stations and other communica-
tions applications. Operating from +3.3V and +1.8V
supplies, the MAX5891 DAC supports update rates of
600Msps using high-speed LVDS inputs while consum-
ing only 298mW of power and offers exceptional
dynamic performance such as 80dBc spurious-free
dynamic range (SFDR) at f
OUT
= 30MHz.
The MAX5891 utilizes a current-steering architecture that
supports a 2mA to 20mA full-scale output current range,
and produces -2dBm to -22dBm full-scale output signal
levels with a double-terminated 50Ω load. The MAX5891
features an integrated +1.2V bandgap reference and
control amplifier to ensure high-accuracy and low-noise
performance. A separate reference input (REFIO) allows
for the use of an external reference source for optimum
flexibility and improved gain accuracy.
The MAX5891 digital inputs accept LVDS voltage lev-
els, and the flexible clock input can be driven differen-
tially or single-ended, AC- or DC-coupled. The
MAX5891 is available in a 68-pin QFN package with an
exposed paddle (EP) and is specified for the extended
(-40°C to +85°C) temperature range.
Refer to the MAX5890* and MAX5889* data sheets for
pin-compatible 14-bit and 12-bit versions of the
MAX5891.
♦
600Msps Output Update Rate
♦
Low Noise Spectral Density: -163dBFS/Hz at
f
OUT
= 36MHz
♦
Excellent SFDR and IMD Performance
SFDR = 80dBc at f
OUT
= 30MHz (to Nyquist)
SFDR = 69dBc at f
OUT
= 130MHz (to Nyquist)
IMD = -94dBc at f
OUT
= 30MHz
IMD = -77dBc at f
OUT
= 130MHz
♦
ACLR = 73dB at f
OUT
= 122.88MHz
♦
2mA to 20mA Full-Scale Output Current
♦
LVDS-Compatible Digital Inputs
♦
On-Chip +1.2V Bandgap Reference
♦
Low 298mW Power Dissipation at 600Msps
♦
Compact (10mm x 10mm) QFN-EP Package
♦
Evaluation Kit Available (MAX5891EVKIT)
Features
MAX5891
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
68 QFN-EP**
PKG
CODE
G6800-4
MAX5891EGK -40°C to +85°C
**EP
= Exposed paddle.
Functional Diagram
MAX5891
OUTP
D0–D15
LVDS DATA
INPUTS
Applications
Base Stations: Single/Multicarrier UMTS,
CDMA, GSM
Communications: Fixed Broadband Wireless
Access, Point-to-Point Microwave
Direct Digital Synthesis (DDS)
Cable Modem Termination Systems (CMTS)
Automated Test Equipment (ATE)
Instrumentation
+1.2V
REFERENCE
DACREF
REFIO
FSADJ
LVDS
RECEIVER
LATCH
600MHz
16-BIT DAC
OUTN
Selector Guide
PART
MAX5889*
MAX5890*
RESOLUTION
(BITS)
12
14
UPDATE RATE
LOGIC INPUT
(Msps)
600
600
LVDS
LVDS
LVDS
CLKP
CLKN
CLK
INTERFACE
POWER
DOWN
PD
MAX5891
16
600
*Future
product—contact factory for availability.
Pin Configuration appears at end of data sheet.
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
16-Bit, 600Msps, High-Dynamic-Performance
DAC with LVDS Inputs
MAX5891
ABSOLUTE MAXIMUM RATINGS
AV
DD1.8
, DV
DD1.8
to AGND, DGND, DACREF,
and CGND.......................................................-0.3V to +2.16V
AV
DD3.3
, DV
DD3.3
, AV
CLK
to AGND, DGND,
DACREF, and CGND.........................................-0.3V to +3.9V
REFIO, FSADJ to AGND, DACREF,
DGND, and CGND ..........................-0.3V to (AV
DD3.3
+ 0.3V)
OUTP, OUTN to AGND, DGND, DACREF,
and CGND .......................................-1.2V to (AV
DD3.3
+ 0.3V)
CLKP, CLKN to AGND, DGND, DACREF,
and CGND..........................................-0.3V to (AV
CLK
+ 0.3V)
PD to AGND, DGND, DACREF,
and CGND.......................................-0.3V to (DV
DD3.3
+ 0.3V)
Digital Data Inputs (D0N–D15N, D0P–D15P) to AGND,
DGND, DACREF, and CGND ..........-0.3V to (DV
DD1.8
+ 0.3V)
Continuous Power Dissipation (T
A
= +70°C) (Note 1)
68-Pin QFN-EP (derate 28.6mW/°C above +70°C)....3333mW
Thermal Resistance
θ
JA
(Note 1) ....................................24°C/W
Operating Temperature Range ..........................-40°C to +85°C
Junction Temperature .....................................................+150°C
Storage Temperature Range ............................-60°C to +150°C
Lead Temperature (soldering, 10s) ................................+300°C
Note 1:
Thermal resistance based on a multilayer board with 4x4 via array in exposed paddle area
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AV
DD3.3
= DV
DD3.3
= AV
CLK
= +3.3V, AV
DD1.8
= DV
DD1.8
= +1.8V, external reference V
REFIO
= +1.2V, output load 50Ω double-ter-
minated, transformer-coupled output, I
OUT
= 20mA, T
A
= -40°C to +85°C, unless otherwise noted. Specifications at T
A
≥
+25°C are
guaranteed by production testing. Specifications at T
A
< +25°C are guaranteed by design and characterization. Typical values are at
T
A
= +25°C.)
PARAMETER
STATIC PERFORMANCE
Resolution
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Full-Scale Gain Error
Gain-Drift Tempco
Full-Scale Output Current
Output Compliance
Output Resistance
Output Capacitance
Output Leakage Current
DYNAMIC PERFORMANCE
Maximum DAC Update Rate
Minimum DAC Update Rate
f
CLK
= 500MHz,
-12dBFS, 20MHz
offset from the
carrier
f
CLK
= 500MHz,
0dBFS
f
OUT
= 36MHz
A
FULL-SCALE
= -3.5dBm
f
OUT
= 151MHz
A
FULL-SCALE
= -6.4dBm
f
OUT
= 36MHz
f
OUT
= 151MHz
600
1
-163
dBFS/Hz
-155
70
64
dB
Msps
Msps
R
OUT
C
OUT
PD = high, power-down mode
I
OUT
Single-ended
INL
DNL
OS
GE
FS
External reference
Internal reference
External reference
2
-1.0
1
5
±1
Measured differentially
Measured differentially
-0.02
-4
16
±3.8
±1.6
±0.001
±1
±130
±100
20
+1.1
+0.02
+4
Bits
LSB
LSB
%FS
%FS
ppm/°C
mA
V
MΩ
pF
µA
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Noise Spectral Density
N
Signal-to-Noise Ratio Over
Nyquist
SNR
2
_______________________________________________________________________________________
16-Bit, 600Msps, High-Dynamic-Performance
DAC with LVDS Inputs
ELECTRICAL CHARACTERISTICS (continued)
(AV
DD3.3
= DV
DD3.3
= AV
CLK
= +3.3V, AV
DD1.8
= DV
DD1.8
= +1.8V, external reference V
REFIO
= +1.2V, output load 50Ω double-ter-
minated, transformer-coupled output, I
OUT
= 20mA, T
A
= -40°C to +85°C, unless otherwise noted. Specifications at T
A
≥
+25°C are
guaranteed by production testing. Specifications at T
A
< +25°C are guaranteed by design and characterization. Typical values are at
T
A
= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
f
CLK
= 200MHz,
0dBFS
Spurious-Free
Dynamic Range to
Nyquist
f
CLK
= 200MHz,
-12dBFS
SFDR
f
CLK
= 500MHz,
0dBFS
f
OUT
= 16MHz
f
OUT
= 30MHz
f
OUT
= 16MHz
f
OUT
= 30MHz
f
OUT
= 16MHz
f
OUT
= 30MHz
f
OUT
= 130MHz
f
OUT
= 200MHz
f
CLK
= 500MHz
Two-Tone IMD
TTIMD
f
CLK
= 500MHz
f
OUT1
= 29MHz,
f
OUT2
= 30MHz,
-6.5dBFS per tone
f
OUT1
= 129MHz,
f
OUT2
= 130MHz,
-6.5dBFS per tone
f
CLK
= 491.52MHz,
f
OUT
= 30.72MHz
f
CLK
= 491.52MHz,
f
OUT
= 122.88MHz
f
CLK
= 491.52MHz,
f
OUT
= 30.72MHz
f
CLK
= 491.52MHz,
f
OUT
= 122.88MHz
Output Bandwidth
REFERENCE
Internal Reference Voltage Range
Reference Input Voltage Range
Reference Input Resistance
Reference Voltage Temperature
Drift
V
REFIO
V
REFIOCR
R
REFIO
TCO
REF
Using external reference
1.14
0.10
1.2
1.2
10
±50
1.26
1.32
V
V
kΩ
ppm/°C
BW
-1dB
(Note 2)
77
MIN
TYP
86
84
76
76
84
80
69
63
-94
dBc
-77
dBc
MAX
UNITS
MAX5891
82
73
dB
74
67
1000
MHz
WCDMA single
carrier
Adjacent Channel
Leakage Power Ratio
ACLR
WCDMA four carriers
_______________________________________________________________________________________
3
16-Bit, 600Msps, High-Dynamic-Performance
DAC with LVDS Inputs
MAX5891
ELECTRICAL CHARACTERISTICS (continued)
(AV
DD3.3
= DV
DD3.3
= AV
CLK
= +3.3V, AV
DD1.8
= DV
DD1.8
= +1.8V, external reference V
REFIO
= +1.2V, output load 50Ω double-ter-
minated, transformer-coupled output, I
OUT
= 20mA, T
A
= -40°C to +85°C, unless otherwise noted. Specifications at T
A
≥
+25°C are
guaranteed by production testing. Specifications at T
A
< +25°C are guaranteed by design and characterization. Typical values are at
T
A
= +25°C.)
PARAMETER
Output Fall Time
Output Rise Time
Output Propagation Delay
Output Settling Time
Glitch Impulse
Output Noise
TIMING CHARACTERISTICS
Input Data Rate
Data Latency
Data to Clock Setup Time
Data to Clock Hold Time
Clock Frequency
Minimum Clock Pulse-Width High
Minimum Clock Pulse-Width Low
Turn-On Time
CMOS LOGIC INPUT (PD)
Input Logic High
Input Logic Low
Input Current
Input Capacitance
LVDS INPUTS
Differential Input High
Differential Input Low
Common-Mode Voltage Range
Differential Input Resistance
Common-Mode Input Resistance
Input Capacitance
Clock Common-Mode Voltage
Minimum Differential Input
Voltage Swing
V
IHLVDS
V
ILLVDS
V
ICMLVDS
R
IDLVDS
R
ICMLVDS
C
INLVDS
CLKP and CLKN are internally biased
1.125
110
3.2
3
AV
CLK
/ 2
0.5
+100
-100
1.375
mV
mV
V
Ω
kΩ
pF
V
V
P-P
V
IH
V
IL
I
IN
C
IN
-5
±1.8
3
0.7 x
DV
DD3.3
0.3 x
DV
DD3.3
+5
V
V
µA
pF
t
SETUP
t
HOLD
f
CLK
t
CH
t
CL
t
SHDN
Referenced to rising edge of clock (Note 4)
Referenced to rising edge of clock (Note 4)
CLKP, CLKN
CLKP, CLKN
CLKP, CLKN
External reference, PD falling edge to
output settle within 1%
0.6
0.6
350
-1.2
2
600
5.5
600
MWps
Clock
cycles
ns
ns
MHz
ns
ns
µs
N
OUT
SYMBOL
t
FALL
t
RISE
t
PD
CONDITIONS
90% to 10% (Note 3)
10% to 90% (Note 3)
Reference to data latency (Note 3)
To 0.025% of the final value (Note 3)
Measured differentially
I
OUT
= 2mA
I
OUT
= 20mA
MIN
TYP
0.4
0.4
2.5
11
1
30
30
MAX
UNITS
ns
ns
ns
ns
pV
•
s
pA/√Hz
ANALOG OUTPUT TIMING (Figure 3)
DIFFERENTIAL CLOCK INPUTS (CLKP, CLKN)
4
_______________________________________________________________________________________
16-Bit, 600Msps, High-Dynamic-Performance
DAC with LVDS Inputs
ELECTRICAL CHARACTERISTICS (continued)
(AV
DD3.3
= DV
DD3.3
= AV
CLK
= +3.3V, AV
DD1.8
= DV
DD1.8
= +1.8V, external reference V
REFIO
= +1.2V, output load 50Ω double-ter-
minated, transformer-coupled output, I
OUT
= 20mA, T
A
= -40°C to +85°C, unless otherwise noted. Specifications at T
A
≥
+25°C are
guaranteed by production testing. Specifications at T
A
< +25°C are guaranteed by design and characterization. Typical values are at
T
A
= +25°C.)
PARAMETER
Minimum Common-Mode Voltage
Maximum Common-Mode
Voltage
Input Resistance
Input Capacitance
POWER SUPPLIES
Analog Supply Voltage Range
Clock Supply Voltage Range
Digital Supply Voltage Range
AV
DD3.3
AV
DD1.8
AV
CLK
DV
DD3.3
DV
DD1.8
f
CLK
= 100MHz, f
OUT
= 16MHz
I
AVDD3.3
Analog Supply Current
I
AVDD1.8
f
CLK
= 500MHz, f
OUT
= 16MHz
f
CLK
= 600MHz, f
OUT
= 16MHz
f
CLK
= 100MHz, f
OUT
= 16MHz
f
CLK
= 500MHz, f
OUT
= 16MHz
f
CLK
= 600MHz, f
OUT
= 16MHz
f
CLK
= 100MHz, f
OUT
= 16MHz
Clock Supply Current
I
AVCLK
f
CLK
= 500MHz, f
OUT
= 16MHz
f
CLK
= 600MHz, f
OUT
= 16MHz
f
CLK
= 100MHz, f
OUT
= 16MHz
I
DVDD3.3
Digital Supply Current
I
DVDD1.8
f
CLK
= 500MHz, f
OUT
= 16MHz
f
CLK
= 600MHz, f
OUT
= 16MHz
f
CLK
= 100MHz, f
OUT
= 16MHz
f
CLK
= 500MHz, f
OUT
= 16MHz
f
CLK
= 600MHz, f
OUT
= 16MHz
f
CLK
= 100MHz, f
OUT
= 16MHz
f
CLK
= 500MHz, f
OUT
= 16MHz
Total Power Dissipation
P
DISS
f
CLK
= 600MHz, f
OUT
= 16MHz
Power-down, clock static low,
data input static
Power-Supply Rejection Ratio
PSRR
(Note 5)
3.135
1.710
3.135
3.135
1.710
3.3
1.8
3.3
3.3
1.8
26.5
26.5
26.5
11.3
50
61
2.8
2.8
2.8
0.2
0.2
0.2
10.6
44
50.5
137
267
298
13
±0.025
µW
%FS
301
mW
50
0.5
mA
3.6
mA
58
28
mA
3.465
1.890
3.465
3.465
1.890
V
V
V
R
CLK
C
CLK
Single-ended
SYMBOL
CONDITIONS
MIN
TYP
1
1.9
5
3
MAX
UNITS
V
V
kΩ
pF
MAX5891
Note 2:
Note 3:
Note 4:
Note 5:
This parameter does not include update-rate-dependent effects of sin(x)/x filtering inherent in the MAX5891.
Parameter measured single-ended with 50Ω double-terminated outputs.
Not production tested. Guaranteed by design.
Parameter defined as the change in midscale output caused by a
±5%
variation in the nominal supply voltages.
_______________________________________________________________________________________
5
模拟电子
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
