February 1996
NDS9957
Dual N-Channel Enhancement Mode Field Effect Transistor
General Description
These N-Channel enhancement mode power field effect
transistors are produced using Fairchild's proprietary, high cell
density, DMOS technology. This very high density process is
especially tailored to minimize on-state resistance, provide
superior switching performance, and withstand high energy
pulses in the avalanche and commutation modes. These
devices are particularly suited for low voltage applications such
as DC motor control and DC/DC conversion where fast
switching, low in-line power loss, and resistance to transients
are needed.
Features
2.6A, 60V. R
DS(ON)
= 0.16
Ω
@ V
GS
= 10V.
High density cell design for extremely low R
DS(ON)
.
High power and current handling capability in a widely used
surface mount package.
Dual MOSFET in surface mount package.
_______________________________________________________________________________
5
4
3
2
1
6
7
8
Absolute Maximum Ratings
Symbol
V
DSS
V
GSS
I
D
P
D
Parameter
Drain-Source Voltage
Gate-Source Voltage
Drain Current - Continuous
- Pulsed
T
A
= 25°C unless otherwise noted
NDS9957
60
± 20
(Note 1a)
Units
V
V
A
± 2.6
± 10
2
Power Dissipation for Dual Operation
Power Dissipation for Single Operation
(Note 1a)
(Note 1b)
(Note 1c)
W
1.6
1
0.9
-55 to 150
°C
T
J
,T
STG
Operating and Storage Temperature Range
THERMAL CHARACTERISTICS
R
θ
JA
R
θ
JC
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Case
(Note 1a)
(Note 1)
78
40
°C/W
°C/W
© 1997 Fairchild Semiconductor Corporation
NDS9957.SAM
Electrical Characteristics
(T
A
= 25°C unless otherwise noted)
Symbol
BV
DSS
I
DSS
I
GSSF
I
GSSR
V
GS(th)
R
DS(ON)
Parameter
Drain-Source Breakdown Voltage
Zero Gate Voltage Drain Current
Gate - Body Leakage, Forward
Gate - Body Leakage, Reverse
Gate Threshold Voltage
Static Drain-Source On-Resistance
Conditions
V
GS
= 0 V, I
D
= 250 µA
V
DS
= 48 V, V
GS
= 0 V
V
GS
= 20 V, V
DS
= 0 V
V
GS
= -20 V, V
DS
= 0 V
V
DS
= V
GS
, I
D
= 250 µA
T
A
= 125°C
V
GS
= 10 V, I
D
= 2.6 A
T
A
= 125°C
V
GS
= 4.5 V, I
D
= 2.1 A
T
A
= 125°C
I
D(on)
g
FS
C
iss
C
oss
C
rss
t
D(on)
t
r
t
D(off)
t
f
Q
g
Q
gs
Q
gd
On-State Drain Current
Forward Transconductance
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn - On Delay Time
Turn - On Rise Time
Turn - Off Delay Time
Turn - Off Fall Time
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
V
DS
= 30 V,
I
D
= 2.6 A, V
GS
= 10 V
V
DD
= 30 V, I
D
= 1 A,
V
GS
= 10 V,R
GEN
= 6
Ω
V
GS
= 10 V, V
DS
= 5 V
V
DS
= 5 V, I
D
= 2.6 A
V
DS
= 30 V, V
GS
= 0 V,
f = 1.0 MHz
10
4
200
60
20
6
11
17
4
7.5
2.8
0.8
20
25
30
15
12
1
0.7
1.5
1.1
0.145
0.25
0.19
0.32
Min
60
1
100
-100
3
2.2
0.16
0.3
0.25
0.5
A
S
pF
pF
pF
ns
ns
ns
ns
nC
nC
nC
Typ
Max
Units
V
µA
nA
nA
V
OFF CHARACTERISTICS
ON CHARACTERISTICS
(Note 2)
Ω
DYNAMIC CHARACTERISTICS
SWITCHING CHARACTERISTICS
(Note 2)
NDS9957.SAM
Electrical Characteristics
(T
A
= 25°C unless otherwise noted)
Symbol
I
S
V
SD
Notes:
1. R
θ
JA
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
θ
JC
is guaranteed by
design while R
θ
CA
is determined by the user's board design.
Parameter
Conditions
Min
Typ
Max
1.7
Units
A
V
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
Maximum Continuos Drain-Source Diode Forward Current
Drain-Source Diode Forward Voltage
V
GS
= 0 V, I
S
= 2.6 A
(Note 2)
0.9
1.2
P
D
(
t
) =
R
θ
J A
t
)
(
T
J
−
T
A
=
R
θ
J C
R
θ
CA
t
)
+
(
T
J
−
T
A
=
I
2
(
t
) ×
R
DS
(
ON
)
D
T
J
Typical R
θ
JA
for single device operation using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:
a. 78
o
C/W when mounted on a 0.5 in
2
pad of 2oz cpper.
b. 125
o
C/W when mounted on a 0.02 in
2
pad of 2oz cpper.
c. 135
o
C/W when mounted on a 0.003 in
2
pad of 2oz cpper.
1a
1b
1c
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
NDS9957.SAM
Typical Electrical Characteristics
10
3
V
GS
=10V
, DRAIN-SOURCE CURRENT (A)
8
6.0 5.0
4.5
DRAIN-SOURCE ON-RESISTANCE
2.5
R
DS(on)
, NORMALIZED
V
GS
= 3.0V
4.0
3.5
2
6
4.0
4.5
3.5
4
1.5
3.0
2
5.0
6.0
10
1
D
2.5
0
0
1
2
3
V
DS
, DRAIN-SOURCE VOLTAGE (V)
4
5
I
0.5
0
2
4
6
I
D
, DRAIN CURRENT (A)
8
10
Figure 1. On-Region Characteristics.
Figure 2. On-Resistance Variation with Gate Voltage
and Drain Current.
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
-50
2.5
DRAIN-SOURCE ON-RESISTANCE
R
DS(on)
, NORMALIZED
R
DS(ON)
, NORMALIZED
V
G S
= 10V
DRAIN-SOURCE ON-RESISTANCE
I
D
= 2.6A
V
GS
= 10 V
2
TJ = 125°C
1.5
25°C
1
-55°C
0.5
-25
0
25
50
75
100
T
J
, JUNCTION TEMPERATURE (°C)
125
150
0
2
4
6
8
10
I
D
, DRAIN CURRENT (A)
Figure 3. On-Resistance Variation
with Temperature.
Figure 4. On-Resistance Variation with Drain
Current and Temperature.
10
1.2
125
V
th
, NORMALIZED
GATE-SOURCE THRESHOLD VOLTAGE
V
DS
= 10V
8
I
D
, DRAIN CURRENT (A)
TJ = -55°C
25
1.1
V
DS
= V
GS
I
D
= 250µA
1
6
0.9
4
0.8
2
0.7
0
1
2
3
4
5
V
GS
, GATE TO SOURCE VOLTAGE (V)
6
0.6
-50
-25
0
25
50
75
100
T , JUNCTION TEMPERATURE (°C)
J
125
150
Figure 5. Transfer Characteristics.
Figure 6. Gate Threshold Variation with
Temperature.
NDS9957.SAM
Typical Electrical Characteristics
(continued)
DRAIN-SOURCE BREAKDOWN VOLTAGE
1.12
I
D
= 250µA
10
V
GS
= 0V
I
S
, REVERSE DRAIN CURRENT (A)
BV
DSS
, NORMALIZED
1.08
1
TJ = 125°C
1.04
25°C
-55°C
0.1
1
0.96
0.01
0.92
-50
-25
0
25
50
75
100
T
J
, JUNCTION TEMPERATURE (°C)
125
150
0.001
0.2
0.4
0.6
0.8
1
1.2
1.4
V
SD
, BODY DIODE FORWARD VOLTAGE (V)
Figure 7. Breakdown Voltage Variation with
Temperature.
Figure 8. Body Diode Forward Voltage Variation
with Current and Temperature.
500
300
200
CAPACITANCE (pF)
10
I
D
= 2.6A
V
GS
, GATE-SOURCE VOLTAGE (V)
V
DS
= 5V
C iss
30V
10V
8
100
6
C oss
50
4
20
f = 1 MHz
V
GS
= 0V
0.2
0.5
1
2
5
10
20
C rss
2
10
0.1
30
60
0
0
2
4
Q
g
, GATE CHARGE (nC)
6
8
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
Figure 9. Capacitance Characteristics.
Figure 10. Gate Charge Characteristics.
V
DD
V
IN
D
t
on
t
off
t
r
90%
R
L
V
OUT
DUT
t
d(on)
t
d(off)
90%
t
f
V
GS
V
OUT
R
GEN
10%
10%
INVERTED
G
90%
S
V
IN
10%
50%
50%
PULSE WIDTH
Figure 11. Switching Test Circuit
Figure 12. Switching Waveforms
NDS9957.SAM
嵌入式系统
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