MT9V124
MT9V124 1/13‐Inch
System‐On‐A‐Chip (SOC)
CMOS Digital Image Sensor
GENERAL DESCRIPTION
ON Semiconductor’s MT9V124 is a 1/13-inch CMOS digital image
sensor with an active-pixel array of 648 (H)
×
488 (V). It includes
sophisticated camera functions such as auto exposure control, auto
white balance, black level control, flicker detection and avoidance,
and defect correction. It is designed for low light performance. It is
programmable through a simple two-wire serial interface. The
MT9V124 produces extraordinarily clear, sharp digital pictures that
make it the perfect choice for a wide range of medical and industrial
applications.
Table 1. KEY PARAMETERS
Parameter
Optical Format
Active Pixels
Pixel Size
Color Filter Array
Shutter Type
Input Clock Range
Output
LVDS
1/13-inch
648
×
488 = 0.3 Mp (VGA)
1.75
μm
RGB Bayer
Electronic Rolling Shutter (ERS)
18–44 MHz
12-bit Packet
30 fps
1.65 V/lux
×
sec
33.4 dB
58 dB
Analog
Supply Voltage
Digital
Digital I/O
Power Consumption
Operating Temperature (Ambient) −T
A
Chief Ray Angle
Package Options
2.5–3.1 V
1.7–1.95 V
1.7–1.95 V or 2.5–3.1 V
55 mW
–30°C to +70°C
24°
Bare die, CSP
Typical Value
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ODCSP25 2.694
×
2.694
CASE 570BN
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
Features
(continued)
•
Integrated Image Flow Processor (IFP) for
•
•
•
•
•
•
•
•
•
•
Single-die Camera Module
One-time Programmable Memory (OTPM)
Automatic Image Correction and
Enhancement, Including Four-channel Lens
Shading Correction
Image Scaling with Anti-aliasing
Supports ITU-R BT.656 Format with Odd
Timing Code
Two-wire Serial Interface Providing Access
to Registers and Microcontroller Memory
Selectable Output Data Format: YCbCr,
565RGB, and RAW8+2-bit, BT656
High Speed Serial Data Output in 12-bit
Packet
Independently Configurable Gamma
Correction
Direct XDMA Access
(Reducing Serial Commands)
Integrated Hue Rotation
±
22
°
Frame Rate, Full Resolution
Responsivity
SNR
MAX
Dynamic Range
Features
•
•
•
•
Superior Low-light Performance
Ultra-low-power
VGA Video at 30fps
Internal Master Clock Generated by On-chip Phase Locked Loop
(PLL) Oscillator
•
Electronic Rolling Shutter (ERS), Progressive Scan
Applications
•
Medical Tools, Device
•
Biometrics
•
Industrial Application
©
Semiconductor Components Industries, LLC, 2010
1
September, 2017 − Rev. 4
Publication Order Number:
MT9V124/D
MT9V124
ORDERING INFORMATION
Table 2. AVAILABLE PART NUMBERS
Part Number
MT9V124D00STCK22DC1−200
MT9V124EBKSTC−CR
Product Description
RGB color die
CSP with 400
μm
coverglass
Orderable Product Attribute Description †
Die Sales, 200
μm
Thickness
Chip Tray without Protective Film
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specification Brochure, BRD8011/D.
FUNCTIONAL DESCRIPTION
See the ON Semiconductor Device Nomenclature
document (TND310/D) for a full description of the naming
convention used for image sensors. For reference
documentation, including information on evaluation kits,
please visit our web site at
www.onsemi.com.
ON Semiconductor’s MT9V124 is a 1/13-inch VGA
CMOS digital image sensor with an integrated advanced
camera system. This camera system features a
microcontroller (MCU), a sophisticated image flow
processor (IFP), and a serial port (using LVDS signaling).
The microcontroller manages all functions of the camera
system and sets key operation parameters for the sensor core
to optimize the quality of raw image data entering the IFP.
The sensor core consists of an active pixel array of
648
×
488 pixels with programmable timing and control
circuitry. It also includes an analog signal chain with
automatic offset correction, programmable gain, and a
10-bit analog-to-digital converter (ADC).
V
DD
V
PP
V
DDIO
V
AA
The entire system-on-a-chip (SOC) has an ultra-low
power operational mode and a superior low-light
performance that is particularly suitable for medical
applications. The MT9V124 features ON Semiconductor’s
breakthrough low-noise CMOS imaging technology that
achieves near-CCD image quality (based on signal-to-noise
ratio and low-light sensitivity) while maintaining the
inherent size, cost, and integration advantages of CMOS.
Architecture Overview
The MT9V124 combines a VGA sensor core with an IFP
to form a stand-alone solution for both image acquisition
and processing. Both the sensor core and the IFP have
internal registers that can be controlled by the user. In
normal operation, an integrated microcontroller
autonomously controls most aspects of operation. The
processed image data is transmitted to the external host
system through an LVDS bus. Figure 1 shows the major
functional blocks of the MT9V124.
Register Bus
Image Data Bus
Pixel Array
(648 x 488)
Column Control
PLL
CCI Serial
Interface
S
DATA
SCLOCK
RAM ROM
uControroller
Serializer
F IFO
Column Control
STANDBY
EXTCLK
Analog
Processing
LVDS_N
LVDS_P
ADC
Digital Image
Processing (SOC)
A
GND
D
GND
Figure 1. MT9V124 Block Diagram
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2
MT9V124
Sensor Core
The MT9V124 has a color image sensor with a Bayer
color filter arrangement and a VGA active-pixel array with
electronic rolling shutter (ERS). The sensor core readout is
10 bits. The sensor core also supports separate analog and
digital gain for all four color channels (R, Gr, Gb, B).
Image Flow Processor (IFP)
The advanced IFP features and flexible programmability
of the MT9V124 can enhance and optimize the image sensor
performance. Built-in optimization algorithms enable the
MT9V124 to operate with factory settings as a fully
automatic and highly adaptable system-on-a-chip (SOC) for
most camera systems.
These algorithms include shading correction, defect
correction, color interpolation, edge detection, color
correction, aperture correction, and image formatting with
cropping and scaling.
Microcontroller Unit (MCU)
The MCU communicates with all functional blocks by
way of an internal ON Semiconductor proprietary bus
interface. The MCU firmware executes the automatic
control algorithms for exposure and white balance.
System Control
The MT9V124 has a phase-locked loop (PLL) oscillator
that can generate the internal sensor clock from the common
system clock. The PLL adjusts the incoming clock
frequency up, allowing the MT9V124 to run at almost any
desired resolution and frame rate within the sensor’s
capabilities.
Low-power consumption is a very important requirement
for all components of wireless devices. The MT9V124
provides power-conserving features, including an internal
soft standby mode and a hard standby mode.
A two-wire serial interface bus enables read and write
access to the MT9V124’s internal registers and variables.
The internal registers control the sensor core, the color
pipeline flow, the output interface, auto white balance
(AWB) and auto exposure (AE).
Output Interface
The output interface block can select either raw data or
processed data. Image data is provided to the host system by
an 8-bit parallel port (up to 22 Mb/sec) or by a serial MIPI
port (264 MHz LVDS clock with 8-bit and 10-bit support).
The parallel output port provides 8-bit YCbCr, YUV, 565
RGB, BT656, processed Bayer data or extended 10-bit
Bayer data achieved using 8 + 2 format.
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MT9V124
System Interfaces
Figure 2 shows typical MT9V124 device connections.
For low-noise operation, the MT9V124 requires separate
power supplies for analog and digital sections. Both power
supply rails should be decoupled from ground using
capacitors as close as possible to the die.
I/O
3
Power
The MT9V124 provides dedicated signals for digital core
and I/O power domains that can be at different voltages. The
PLL and analog circuitry require clean power sources.
Table 3, “Pin Descriptions,” provides the signal descriptions
for the MT9V124.
OTPM
Power
(optimal)
Digital
Core
(optimal)
Analog
power
V
DD
V
PP
R
PULL−UP2
Two−wire
serial interface
Active HIGH standby mode
External clock in
(18–44 MHz)
S
DATA
S
CLK
STANDBY
EXTCLK
V
DD
_IO
LVDS_N
R
t
140
Ω
LVDS_P
Serial
interface
GND, GND_PLL
A
GND
V
DD
_IO
3, 4
V
DD4
V
AA4
Notes: 1. This typical configuration shows only one scenario out of multiple possible variations for this sensor.
2. ON Semiconductor recommends a 1.5 kΩ resistor value for the two-wire serial interface R
PULL-UP;
however, greater
values may be used for slower transmission speed.
3. All inputs must be configured with V
DD_
IO.
4. ON Semiconductor recommends that 0.1
μF
and 1
μF
decoupling capacitors for each power supply are mounted as
close as possible to the module (Low-Z path). Actual values and numbers may vary depending on layout and design
considerations, such as capacitor effective series resistance (ESR), dielectric, or power supply source impedance.
5. LVDS output requires termination resistor (140
Ω)
to be placed closely at the sensor side.
Figure 2. Typical Configuration (Connection)
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4
V
AA
MT9V124
Signal Descriptions
Table 3. PIN DESCRIPTIONS
MT9V124
Sensor Signal
Name
EXTCLK
STANDBY
SCLK
S
DATA
LVDS_P
LVDS_N
V
DD
V
AA
, V
DD
_PLL
V
DD
_IO
D
GND
, GND_IO,
GND_PLL
A
GND
V
PP
DNU
Module Signal
Name
EXTCLK
STBY
SCLK
S
DATA
LVDS_P
LVDS_N
V
DD
V
AA
V
DD
_IO
D
GND
A
GND
V
PP
DNU
Ball Number
E2
A2
D4
E4
E1
D2
C2, D5
C1
C3
B3, B5, D1
B1
A1
A3,A4,A5,B2,B4,
C4,C5,D3,E3,E5
Type
Input
Input
Input
I/O
Output
Output
Supply
Supply
Supply
Supply
Supply
Supply
Input clock signal
Description
Controls sensor’s standby mode, active HIGH
Two-wire serial interface clock
Two-wire serial interface data
LVDS positive output
LVDS negative output
Digital power (TYP 1.8 V)
Analog and PLL power (TYP 2.8 V)
I/O power supply (TYP 1.8 V)
Digital, I/O, and PLL ground
Analog ground
OTPM power
1
2
3
4
5
A
VPP
B
AGND
C
VAA
D
GND
E
LVDS_P EXTCLK
DNU
SDATA
DNU
LVDS_N
DNU
SCLK
VDD
VDD
VDD_IO
DNU
DNU
DNU
GND
DNU
GND
STDBY
DNU
DNU
DNU
Figure 3. 25-ball Assignments (Top View)
Power-On Reset
The MT9V124 includes a power-on reset feature that
initiates a reset upon power-up. A soft reset is issued by
writing commands through the two-wire serial interface.
Standby
The MT9V124 supports two different standby modes:
•
Hard standby mode
•
Soft standby mode
The hard standby mode is invoked by asserting
STANDBY pin. It then disables all the digital logic within
the image sensor, and only supports being awoken by
de-asserting the STANDBY pin. The soft standby mode is
enabled by a single register access, which then disables the
sensor core and most of the digital logic. However, the
two-wire serial interface is kept alive, which allows the
image sensor to be awoken via a serial register access.
All output signal status during standby are shown in
Table 4.
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