CAT34TS04
Digital Output Temperature
Sensor with On-board SPD
EEPROM
Description
The CAT34TS04 is a combination Temperature Sensor (TS) and
4−Kb of Serial Presence Detect (SPD) EEPROM, which implements
the JEDEC TSE2004av DDR4 specification and supports the Standard
(100 kHz), Fast (400 kHz) and Fast Plus (1 MHz) I
2
C protocols.
The TS measures temperature at least 10 times every second.
Temperature readings can be retrieved by the host via the serial
interface, and are compared to high, low and critical trigger limits
stored into internal registers. Over or under limit conditions can be
signaled on the open−drain EVENT pin.
One of the two available 2−Kb SPD EEPROM banks (referred to as
SPD pages in the TSE2004av specification) is activated for access at
power−up. After power−up, banks can be switched via software
command. Each of the four 1−Kb SPD EEPROM blocks can be Write
Protected by software command.
Features
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TDFN−8
VP2 SUFFIX
CASE 511AK
UDFN−8
HU4 SUFFIX
CASE 517AZ
PIN CONFIGURATION
A
0
A
1
A
2
V
SS
TDFN (VP2), UDFN (HU4)
For the location of Pin 1, please consult the
corresponding package drawing.
1
(Top View)
V
CC
EVENT
SCL
SDA
•
•
•
•
•
•
•
•
•
•
JEDEC TSE2004av Compliant Temperature Sensor
Temperature Range:
−20°C
to +125°C
DDR4 DIMM Compliant SPD EEPROM
Supply Range: 1.7 V
−
5.5 V (SPD EEPROM) and
2.2 V
−
5.5 V (TS)
I
2
C / SMBus Interface
Schmitt Triggers and Noise Suppression Filters on SCL and SDA
Inputs
16−Byte Page Write Buffer
Low Power CMOS Technology
2 x 3 x 0.75 mm TDFN Package and 2 x 3 x 0.5 mm UDFN Package
These Devices are Pb−Free and are RoHS Compliant
V
CC
MARKING DIAGRAM
4TA
ALL
YM
G
4UA
ALL
YM
G
TDFN−8
UDFN−8
4TA, 4UA = Specific Device Code
A
= Assembly Location Code
LL
= Assembly Lot Number (Last Two Digits)
Y
= Production Year (Last Digit)
M
= Production Month (1
−
9, O, N, D)
G
= Pb−Free Package
= Pin 1 Indicator
PIN FUNCTIONS
SCL
CAT34TS04
Pin Name
A
0
, A
1
, A
2
EVENT
SDA
SCL
EVENT
V
SS
V
CC
V
SS
DAP
Function
Device Address Input
Serial Data Input/Output
Serial Clock Input
Open−drain Event Output
Power Supply
Ground
Backside Exposed DAP at V
SS
A
2
, A
1
, A
0
SDA
Figure 1. Functional Symbol
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 18 of this data sheet.
©
Semiconductor Components Industries, LLC, 2013
October, 2013
−
Rev. 6
1
Publication Order Number:
CAT34TS04/D
CAT34TS04
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameter
Operating Temperature
Storage Temperature
Voltage on any pin (except A
0
) with respect to Ground (Note 1)
Voltage on pin A
0
with respect to Ground
Rating
−45
to +130
−65
to +150
−0.5
to +6.5
−0.5
to +10.5
Units
°C
°C
V
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The DC input voltage on any pin should not be lower than
−0.5
V or higher than V
CC
+ 0.5 V. The A
0
pin can be raised to a HV level for SWP
command execution. SCL and SDA inputs can be raised to the maximum limit, irrespective of V
CC
.
Table 2. RELIABILITY CHARACTERISTICS
Symbol
N
END
(Note 2)
T
DR
Parameter
Endurance (EEPROM)
Data Retention (EEPROM)
Min
1,000,000
100
Units
Write Cycles
Years
2. Page Mode, V
CC
= 2.5 V, 25°C
Table 3. TEMPERATURE CHARACTERISTICS
(V
CC
= 2.2 V to 3.6 V, T
A
=
−20°C
to +125°C, unless otherwise specified)
Parameter
Temperature Reading Error
Test Conditions/Comments
+75°C
≤
T
A
≤
+95°C, active range
+40°C
≤
T
A
≤
+125°C, monitor range
−20°C
≤
T
A
≤
+125°C, sensing range
ADC Resolution
Temperature Resolution
Conversion Time
Thermal Resistance (Note 3)
q
JA
Junction−to−Ambient (Still Air)
Max
±1.0
±2.0
±3.0
12
0.0625
100
92
Unit
°C
°C
°C
Bits
°C
ms
°C/W
3. Power Dissipation is defined as P
J
= (T
J
−
T
A
)/q
JA
, where T
J
is the junction temperature and T
A
is the ambient temperature. The thermal
resistance value refers to the case of a package being used on a standard 2−layer PCB.
Table 4. D.C. OPERATING CHARACTERISTICS
(V
CC
= 2.2 V to 3.6 V, T
A
=
−20°C
to +125°C, unless otherwise specified)
Symbol
I
CC
I
SHDN
I
LKG
V
IL
V
IH
V
OL1
(Note 4)
V
OL2
Parameter
Supply Current
Test Conditions/Comments
TS active, SPD and Bus idle
SPD Write, TS shut−down
Standby Current
I/O Pin Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output Low Voltage
I
OL
= 3 mA, V
CC
> 2.2 V
I
OL
= 1 mA, V
CC
< 2.2 V
TS shut−down; SPD and Bus idle
Pin at GND or V
CC
−0.5
0.7 x V
CC
Min
Max
1000
1000
10
2
0.3 x V
CC
V
CC
+ 0.5
0.4
0.2
Unit
mA
mA
mA
mA
V
V
V
V
4. The device is able to handle R
L
values corresponding to the specified rise time (see Figure 2).
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2
CAT34TS04
Table 5. A.C. CHARACTERISTICS
(V
CC
= 2.2 V to 3.6 V, T
A
=
−20°C
to +125°C)
Symbol
F
SCL
(Note 5)
t
HIGH
t
LOW
t
TIMEOUT
(Note 6)
t
R
(Note 7)
t
F
(Note 7)
t
SU:DAT
t
SU:STA
t
HD:STA
t
SU:STO
t
BUF
t
HD:DAT
t
DH
(Note 7)
T
i
t
WR
t
PU
(Note 8)
Clock Frequency
High Period of SCL Clock
Low Period of SCL Clock
SMBus SCL Clock Low Timeout
SDA and SCL Rise Time
SDA and SCL Fall Time
Input Data Setup Time
START Condition Setup Time
START Condition Hold Time
STOP Condition Setup Time
Bus Free Time Between STOP and START
Input Data Hold Time
Output Data Hold Time
Noise Pulse Filtered at SCL and SDA Inputs
Write Cycle Time
Power-Up Delay to Valid Temperature Recording
50
260
260
260
500
0
120
300
50
5
100
Parameter
Min
0.01
260
500
25
35
120
120
Max
1
Units
MHz
ns
ns
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
5. Timing reference points are set at 30%, respectively 70% of V
CC
, as illustrated in Figure 5. Bus loading must be such as to allow meeting
the V
IL
and V
OL
as well as all other timing requirements. The minimum clock frequency of 10 kHz is an SMBus recommendation; the minimum
operating clock frequency is limited only by the SMBus time−out. The device also meets the Fast and Standard I
2
C specifications, except
that T
i
and t
DH
are shorter, as required by the 1 MHz Fast Plus protocol.
6. For the CAT34TS04, the interface will reset itself and will release the SDA line if the SCL line stays low beyond the t
TIMEOUT
limit. The time−out
count takes place when SCL is low in the time interval between START and STOP.
7. In a “Wired−OR” system (such as I
2
C or SMBus), SDA rise time is determined by bus loading. Since each bus pull−down device must be
able to sink the (external) bus pull−up current (in order to meet the V
IL
and/or V
OL
limits), it follows that SDA fall time is inherently faster than
SDA rise time. SDA rise time can exceed the standard recommended t
R
limit, as long as it does not exceed t
LOW
−
t
DH
−
t
SU:DAT
, where t
LOW
and t
DH
are actual values (rather than spec limits). A shorter t
DH
leaves more room for a longer SDA t
R
, allowing for a more capacitive bus
or a larger bus pull−up resistor.
8. The first valid temperature recording can be expected after t
PU
at nominal supply voltage.
Table 6. PIN CAPACITANCE
(T
A
= 25°C, V
CC
= 3.6 V, f = 1 MHz)
Symbol
C
IN
Parameter
SDA, EVENT Pin Capacitance
Input Capacitance (other pins)
Test Conditions/Comments
V
IN
= 0
V
IN
= 0
Min
Max
8
6
Unit
pF
pF
PULL−UP RESISTANCE (kW)
V
CC
10
300 ns Rise Time
SDA
1
120 ns Rise Time
C
L
V
SS
0.1
10
100
LOAD CAPACITANCE (pF)
R
L
Figure 2. Pull−up Resistance vs. Load Capacitance
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CAT34TS04
Pin Description
SCL:
The Serial Clock input pin accepts the Serial Clock
generated by the Master (Host).
SDA:
The Serial Data I/O pin receives input data and transmits
data stored in SPD memory or in the TS registers. In transmit
mode, this pin is open drain. Data is acquired on the positive
edge, and is delivered on the negative edge of SCL.
A0, A1 and A2:
The Address pins accept the device address.
These pins have on−chip pull−down resistors.
EVENT:
The open−drain EVENT pin can be programmed
to signal over/under temperature limit conditions.
Power−On Reset (POR)
The CAT34TS04 incorporates Power−On Reset (POR)
circuitry which protects the device against powering up to an
undetermined logic state. As V
CC
exceeds the POR trigger
level, the TS component will power up into conversion
mode and the SPD component will power up into standby
mode. Both the TS and SPD components will power down
into Reset mode when V
CC
drops below the POR trigger
level. This bi−directional POR behavior protects the
CAT34TS04 against brown−out failure following a
temporary loss of power. The POR trigger level is set below
the minimum operating V
CC
level.
Device Interface
The CAT34TS04 supports the Inter−Integrated Circuit
2
C) and the System Management Bus (SMBus) data
(I
transmission protocols. These protocols describe serial
communication between transmitters and receivers sharing a
2−wire data bus. Data
flow
is controlled by a Master device,
which generates the serial clock and the START and STOP
conditions. The CAT34TS04 acts as a Slave device. Master
and Slave alternate as transmitter and receiver. Up to 8
CAT34TS04 devices may be present on the bus
simultaneously, and can be individually addressed by
matching the logic state of the address inputs A0, A1, and A2.
I
2
C/SMBus Protocol
The I
2
C/SMBus uses two ‘wires’, one for clock (SCL) and
one for data (SDA). The two wires are connected to the V
CC
supply via pull−up resistors. Master and Slave devices
connect to the bus via their respective SCL and SDA pins.
The transmitting device pulls down the SDA line to
‘transmit’ a ‘0’ and releases it to ‘transmit’ a ‘1’.
Data transfer may be initiated only when the bus is not
busy (see A.C. Characteristics).
During data transfer, the SDA line must remain stable
while the SCL line is HIGH. An SDA transition while SCL
is HIGH will be interpreted as a START or STOP condition
(Figure 3).
START
The START condition precedes all commands. It consists
of a HIGH to LOW transition on SDA while SCL is HIGH.
The START acts as a ‘wake−up’ call to all Slaves. Absent a
START, a Slave will not respond to commands.
STOP
The STOP condition completes all commands. It consists
of a LOW to HIGH transition on SDA while SCL is HIGH.
The STOP tells the Slave that no more data will be written
to or read from the Slave.
Device Addressing
The Master initiates data transfer by creating a START
condition on the bus. The Master then broadcasts an 8−bit
serial Slave address. The first 4 bits of the Slave address (the
preamble) determine whether the command is intended for
the Temperature Sensor (TS) or the EEPROM. The next 3
bits, A2, A1 and A0, select one of 8 possible Slave devices.
The last bit, R/W, specifies whether a Read (1) or Write (0)
operation is being performed.
Acknowledge
A matching Slave address is acknowledged (ACK) by the
Slave by pulling down the SDA line during the 9
th
clock
cycle (Figure 4). After that, the Slave will acknowledge all
data bytes sent to the bus by the Master. When the Slave is
the transmitter, the Master will in turn acknowledge data
bytes in the 9
th
clock cycle. The Slave will stop transmitting
after the Master does not respond with acknowledge
(NoACK) and then issues a STOP. Bus timing is illustrated
in Figure 5.
SDA
SCL
START BIT
STOP BIT
Figure 3. Start/Stop Timing
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CAT34TS04
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
Figure 4. Acknowledge Timing
t
F
SCL
70%
t
SU:STA
SDA IN
70%
30%
t
HIGH
70%
30%
t
HD:DAT
70%
t
SU:DAT
30%
t
DH
SDA OUT
70%
30%
30%
t
R
70%
t
SU:STO
70%
t
BUF
70%
t
LOW
70%
30%
t
HD:STA
Figure 5. Bus Timing
Table 7. COMMAND SET
(Notes 9, 10)
Function Specific Preamble
Function
Read Temperature Registers
Write Temperature Registers
Read EE Memory
Write EE Memory
Set Write Protection, block 0
Set Write Protection, block 1
Set Write Protection, block 2
Set Write Protection, block 3
Clear All Write Protection
Read Protection Status, block 0
Read Protection Status, block 1
Read Protection Status, block 2
Read Protection Status, block 3
Set SPD Page Address to 0
(Select Lower Bank)
Set SPD Page Address to 1
(Select Upper Bank)
Read SPD Page Address
Reserved
Abbr
RTR
WTR
RSPD
WSPD
SWP0
SWP1
SWP2
SWP3
CWP
RPS0
RPS1
RPS2
RPS3
SPA0
SPA1
RPA
−
0
1
1
0
0
1
1
0
0
0
1
1
0
1
1
1
0
0
0
0
1
0
0
0
0
1
1
1
1
0
1
0
1
1
0
1
0
0
1
0
1
0
1
0
LSA2
LSA1
LSA0
b7
0
b6
0
b5
1
b4
1
b3
LSA2
Select Address
b2
LSA1
b1
LSA0
R/W_n
b0
1
0
1
0
0
0
0
0
0
1
1
1
1
0
0
1
V
HV
V
HV
V
HV
V
HV
V
HV
0, 1 or V
HV
0, 1 or V
HV
0, 1 or V
HV
0, 1 or V
HV
0, 1 or V
HV
0, 1 or V
HV
0, 1 or V
HV
0 or 1
0 or 1
A0 Pin
All Other Encodings
9. LSAx stands for Logic State of Address pin x.
10. If V
HV
is not applied on the A0 pin during SWP/CWP commands, the CAT34TS04 will respond with NoACK after the 3rd byte and will not
execute the SWP/CWP instruction. During RPS/SPA/RPA commands the state of pin A0 must be stable for the duration of the sequence.
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