LH5496/96H
FEATURES
•
Fast Access Times:
15 */20/25/35/50/65/80 ns
•
Full CMOS Dual Port Memory Array
•
Fully Asynchronous Read and Write
•
Expandable-in Width and Depth
•
Full, Half-Full, and Empty Status Flags
•
Read Retransmit Capability
•
TTL Compatible I/O
•
Packages:
28-Pin, 300-mil PDIP
28-Pin, 600-mil PDIP
32-Pin PLCC
•
Pin and Functionally Compatible with IDT7201
FUNCTIONAL DESCRIPTION
The LH5496/96H are dual port memories with internal
addressing to implement a First-In, First-Out algorithm.
Through an advanced dual port architecture, they provide
fully asynchronous read/write operation. Empty, Full, and
Half-Full status flags are provided to prevent data over-
flow and underflow. In addition, internal logic provides for
unlimited expansion in both word size and depth.
Read and write operations automatically access se-
quential locations in memory in that data is read out in the
same order that it was written, that is on a First-In,
First-Out basis. Since the address sequence is internally
predefined, no external address information is required
for the operation of this device. A ninth data bit is provided
for parity or control information often needed in commu-
nication applications.
Empty, Full, and Half-Full status flags monitor the
extent to which data has been written into the FIFO, and
prevent improper operations (i.e., Read if the FIFO is
empty, or Write if the FIFO is full). A retransmit feature
resets the Read address pointer to its initial position,
thereby allowing repetitive readout of the same data.
Expansion In and Expansion Out pins implement an
expansion scheme that allows individual FIFOs to be
cascaded to greater depth without incurring additional
latency (bubblethrough) delays.
* LH5496 only.
NC
CMOS 512
×
9 FIFO
PIN CONNECTIONS
28-PIN PDIP
W
D
8
D
3
D
2
D
1
D
0
XI
FF
Q
0
Q
1
Q
2
Q
3
Q
8
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
D
4
D
5
D
6
D
7
FL/RT
RS
EF
XO/HF
Q
7
Q
6
Q
5
Q
4
R
5496-1D
TOP VIEW
Figure 1. Pin Connections for PDIP Packages
V
CC
32-PIN PLCC
TOP VIEW
D
3
D
8
4
D
2
D
1
D
0
XI
FF
Q
0
Q
1
NC
Q
2
5
6
7
8
9
10
11
12
13
3
2
1
32 31 30
29
28
27
26
25
24
23
22
21
D
6
D
7
NC
FL/RT
RS
EF
XO/HF
Q
7
Q
6
14 15 16 17 18 19 20
Q
4
D
4
V
SS
NC
Q
3
Q
8
Q
5
R
D
5
W
5496-2D
Figure 2. Pin Connections for PLCC Package
1
LH5496/96H
CMOS 512
×
9 FIFO
RS
RESET
LOGIC
INPUT
PORT
CONTROL
WRITE
POINTER
DATA INPUTS
D
0
- D
8
OUTPUT
PORT
CONTROL
READ
POINTER
W
R
DUAL-PORT
RAM
ARRAY
512 x 9
...
DATA OUTPUTS
Q
0
- Q
8
FLAG
LOGIC
EF
FF
FL/RT
XI
EXPANSION
LOGIC
XO/HF
5496-3
Figure 3. LH5496/96H Block Diagram
PIN DESCRIPTIONS
PIN
PIN TYPE *
DESCRIPTION
PIN
PIN TYPE *
DESCRIPTION
D
0
– D
8
Q
0
– Q
8
W
R
EF
FF
I
O/Z
I
I
O
O
Input Data Bus
Output Data Bus
Write Request
Read Request
Empty Flag
Full Flag
XO/HF
XI
FL/RT
RS
V
CC
V
SS
O
I
I
I
V
V
Expansion Out/Half-Full Flag
Expansion In
First Load/Retransmit
Reset
Positive Power Supply
Ground
* I = Input, O = Output, Z = High-Impedance, V = Power Voltage Level
2
CMOS 512
×
9 FIFO
LH5496/96H
ABSOLUTE MAXIMUM RATINGS
1
PARAMETER
RATING
Supply Voltage to V
SS
Potential
Signal Pin Voltage to V
SS
Potential
3
DC Output Current
2
Storage Temperature Range
Power Dissipation (Package Limit)
DC Voltage Applied To Outputs In High-Z State
–0.5 V to 7 V
–0.5 V to V
CC
+ 0.5 V (not to exceed 7 V)
±50
mA
–65
o
C to 150
o
C
1.0 W
–0.5 V to Vcc + 0.5 V (not to exceed 7 V)
NOTES:
1. Stresses greater than those listed under ‘Absolute Maximum Ratings’ may cause permanent damage to the device.
This is a device stress rating for transient conditions only. Functional operation at these or any other conditions above
those indicated in the ‘Operating Range’ of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. Outputs should not be shorted for more than 30 seconds. No more than one output should be shorted at any time.
3. Negative undershoots of 1.5 V in amplitude are permitted for up to 10 ns once per cycle.
OPERATING RANGE
SYMBOL
PARAMETER
MIN
MAX
UNIT
o
C
o
C
T
A
T
A
V
CC
V
SS
V
IL
V
IH
Temperature, Ambient, LH5496
Temperature, Ambient, LH5496H
Supply Voltage
Supply Voltage
Logic ‘0’ Input Voltage
1
Logic ‘1’ Input Voltage
0
–40
4.5
0
–0.5
2.0
70
85
5.5
0
0.8
V
CC
+ 0.5
V
V
V
V
NOTE:
1. Negative undershoots of 1.5 V in amplitude are permitted for up to 10 ns once per cycle.
DC ELECTRICAL CHARACTERISTICS
(Over Operating Range)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
I
LI
I
LO
V
OH
V
OL
I
CC
I
CC2
I
CC3
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
Average Supply Current
1
Average Standby Current
1
Power Down Current
1
V
CC
= 5.5 V, V
IN
= 0 V to V
CC
R
≥
V
IH
, 0 V
≤
V
OUT
≤
V
CC
I
OH
= –2.0 mA
I
OL
= 8.0 mA
Measured at f = 40 MHz
All Inputs = V
IH
All Inputs = V
CC
– 0.2 V
–10
–10
2.4
10
10
µA
µA
V
0.4
100
15
5
V
mA
mA
mA
NOTE:
1. I
CC
, I
CC2
, and I
CC3
are dependent upon actual output loading and cycle rates. Specified values are with outputs open.
3
LH5496/96H
CMOS 512
×
9 FIFO
AC TEST CONDITIONS
PARAMETER
RATING
+5 V
1.1 k
Ω
DEVICE
UNDER
TEST
680
Ω
Input Pulse Levels
Input Rise and Fall Times (10% to 90%)
Input Timing Reference Levels
Output Reference Levels
Output Load, Timing Tests
V
SS
to 3 V
5 ns
1.5 V
1.5 V
Figure 4
30 pF
*
CAPACITANCE
1,2
PARAMETER
RATING
*
5 pF
7 pF
INCLUDES JIG & SCOPE CAPACITANCES
5496-4
C
IN
(Input Capacitance)
C
OUT
(Output Capacitance)
Figure 4. Output Load Circuit
NOTES:
1. Sample tested only.
2. Capacitances are maximum values at 25
o
C measured at 1.0 MHz
with V
IN
= 0 V.
4
CMOS 512
×
9 FIFO
LH5496/96H
AC ELECTRICAL CHARACTERISTICS
1
(Over Operating Range)
t
A
= 15 ns
2
t
A
= 20 ns t
A
= 25 ns t
A
= 35 ns t
A
= 50 ns t
A
= 65 ns
SYMBOL
PARAMETER
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN
MAX
t
A
= 80 ns
MIN MAX
UNIT
READ CYCLE TIMING
t
RC
t
A
t
RR
t
RPW
t
RLZ
t
WLZ
t
DV
t
RHZ
Read Cycle Time
Access Time
Read Recover Time
Read Pulse Width
3
25
–
10
15
5
10
5
–
–
15
–
–
–
–
–
15
30
–
10
20
5
10
5
–
–
20
–
–
–
–
–
15
35
–
10
25
5
10
5
–
–
25
–
–
–
–
–
15
45
–
10
35
5
10
5
–
–
35
–
–
–
–
–
15
65
–
15
50
5
10
5
–
–
50
–
–
–
–
–
20
80
–
15
65
5
10
5
–
–
65
–
–
–
–
–
30
100
–
15
80
10
20
5
–
–
80
–
–
–
–
–
30
ns
ns
ns
ns
ns
ns
ns
ns
Data Bus Active from Read LOW
4
Data Bus Active from Write
HIGH
4,5
Data Valid from Read Pulse HIGH
Data Bus High-Z from Read
4
HIGH
Write Cycle Time
Write Pulse Width
Data Setup Time
Data Hold Time
Reset Cycle Time
Reset Pulse Width
3
3
WRITE CYCLE TIMING
t
WC
t
WPW
t
WR
t
DS
t
DH
t
RSC
t
RS
t
RSR
t
RRSS
t
WRSS
t
RTC
t
RT
t
RTR
t
EFL
t
HFH,FFH
t
REF
t
RFF
t
WEF
t
WFF
t
WHF
t
RHF
t
XOL
t
XOH
t
XI
t
XIR
t
XIS
25
15
10
10
0
25
15
10
15
15
25
3
–
–
–
–
–
–
–
–
–
–
–
–
–
25
25
20
20
20
20
25
25
18
18
–
–
–
30
20
10
10
0
30
20
10
20
20
30
20
10
–
–
–
–
–
–
–
–
–
–
20
10
10
–
–
–
–
–
–
–
–
–
–
–
–
–
30
30
25
25
25
25
30
30
20
20
–
–
–
35
25
10
10
0
35
25
10
25
25
35
25
10
–
–
–
–
–
–
–
–
–
–
25
10
10
–
–
–
–
–
–
–
–
–
–
–
–
–
35
35
25
25
25
25
35
35
25
25
–
–
–
45
35
10
15
0
45
35
10
35
35
45
35
10
–
–
–
–
–
–
–
–
–
–
35
10
15
–
–
–
–
–
–
–
–
–
–
–
–
–
45
45
35
35
35
35
45
45
35
35
–
–
–
65
50
15
20
0
65
50
15
50
50
65
50
15
–
–
–
–
–
–
–
–
–
–
50
10
15
–
–
–
–
–
–
–
–
–
–
–
–
–
65
65
45
45
45
45
65
65
50
50
–
–
–
80
65
15
20
5
80
65
15
65
65
80
65
15
–
–
–
–
–
–
–
–
–
–
65
10
15
–
–
–
–
–
–
–
–
–
–
–
–
–
80
80
60
60
60
60
80
80
65
65
–
–
–
100
80
15
20
5
100
80
15
80
80
100
80
15
–
–
–
–
–
–
–
–
–
–
80
10
15
–
–
–
–
–
–
–
–
–
–
–
–
–
100
100
60
60
60
60
100
100
80
80
–
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Recovery Time
RESET TIMING
Reset Recovery Time
Read HIGH to RS HIGH
Write HIGH to RS HIGH
Retransmit Cycle Time
Retransmit Pulse Width
Retransmit Recovery Time
Reset LOW to Empty Flag LOW
Reset LOW to Half-Full and Full
Flags HIGH
Read LOW to Empty Flag LOW
Read HIGH to Full Flag HIGH
Write HIGH to Empty Flag HIGH
Write LOW to Full Flag LOW
Write LOW to Half-Full Flag LOW
Read HIGH to Half-Full Flag HIGH
Expansion Out LOW
Expansion Out HIGH
Expansion In Pulse Width
Expansion In Recovery Time
Expansion in Setup Time
RETRANSMIT TIMING
15
10
–
–
–
–
–
–
–
–
–
–
15
10
7
FLAG TIMING
EXPANSION TIMING
NOTES:
1. LH5496 only.
2. All timing measurements performed at ‘AC Test Condition’ levels.
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
