NJG1707PG1
800MHz TDMA FRONT-END GaAs MMIC
nGENERAL
DESCRIPTION
NJG1707PG1 is a front-end IC for a digital cellular phone of
800MHz band. A 2x6 antenna switches and a low noise
amplifier are included.
The parallel control signals of three bits logic connect T/R
circuits to internal two antennas or external two antennas. The
termination ports with external matching circuits make low
interference between diversity antennas.
The ultra small & thin FFP32-G1 package is adopted.
nFEATURES
•Ultra
small & thin package
•Antenna
Switch
lLow
voltage operation
lLow
current consumption
lLow
insertion loss
lLow
Adjacent Channel
Leakage Power
•Low
Noise Amplifier
lLow
voltage operation
lLow
current consumption
lSmall
signal gain
lLow
noise figure
lHigh
input IP3
nPIN
CONFIGURATION
AN T2
GND
nPACKAGE
OUTLINE
NJG1707PG1
FFP32-G1 (Mount Size: 4.5x4.5x0.85mm)
-2.5V (Tx only) and +3.5V
10uA typ. (Tx Mode, P
in
=30dBm), 2uA typ. (Rx Mode, P
in
=10dBm)
0.5dB typ. @(Tx-ANT1, Tx-EXT1) f
in
=960MHz, P
in
=30dBm
-63dBc typ. @ V
DD
=+3.5V, V
SS
=-2.5V, f
in
=960MHz, P
in
=30dBm
+2.7V typ.
+2.7mA typ.
17.5dB typ. @f=820MHz
1.4dB typ. @ f=820MHz
IIP3=-4.5dBm typ. OIP3=+13dBm typ. @f=820MHz+820.1MHz
FFP32 Type
(Top View)
AN T1
TE R2
17
GND
GND
24
23
22
21
20
19
18
TER1
GND(LN A)
GND
RX
25
SW 5
26
SW 6
16
GND
15
TX
SW 1
SW 4-1
SW 3 SW 7
14
GND(LN A)
27
SW 8
13
GND
LNAIN
28
SW 4-2
EXT1
GND
29
12
SW 9
GND
LNAOUT
30
11
SW 2
EXT2
EXTCAP
31
ANT-SW CONTROL VO LTAGE
10
GND
VDD
A NT-SW
GND
32
1
DECO RDER
9
2
3
4
5
6
7
8
GND
GN D
GN D
CTL1
CTL2
CTL3
GN D
VSS
-1-
NJG1707PG1
nABSOLUTE
MAXIMUM RATINGS
(T
a
=25°C)
PARAMETER
Supply Voltage 1
Supply Voltage 2
Supply Voltage 3
Control Voltage
Input Power
SYMBOL
V
DD1
V
DD2
V
SS
V
CTL
P
in
CONDTIONS
V
DD
Terminal
LNAOUT Terminal
V
SS
Terminal
CTL1, CTL2, CTL3 Terminals
TX, ANT1, EXT1 Terminals
RX, ANT2, EXT2 Terminals
LNAIN Terminal
RATINGS
6.0
5.0
-4.0~+0.3
6.0
37
28
10
600
-40~+85
-55~+125
UNITS
V
V
V
V
dBm
dBm
dBm
mW
°C
°C
Power Dissipation
Operating
Temperature
Storage
Temperature
P
D
T
opr
T
stg
nELECTRICAL
CHARACTERISTICS 1 [ANTENNA SWITCH DC CHARACTERISTICS]
General Conditions: T
a
=25°C, V
DD
=3.5V, V
SS
=-2.5V
TX, RX, ANT1, ANT2, EXT1, EXT2: terminated (50Ω)
TER1, TER2 : grounded by 10pF capacitor
PARAMETER
Positive Supply Voltage
Negative Supply Voltage
Current Consumption 1
Current Consumption 2
Current Consumption 3
Current Consumption 4
Control Voltage (H)
Control Voltage (L)
Control Current
Control terminal Input
Impedance
SYMBOL
V
DD
V
SS
I
DD1
I
SS1
I
DD2
I
SS2
V
CTL(H)
V
CTL(L)
I
CTL
R
in
CONDITIONS
V
DD
Terminal
V
SS
Terminal
V
DD
Terminal
Rx Mode, No RF Signal
V
SS
Terminal
Rx Mode, No RF Signal
V
DD
Terminal, f
in
=0.1~2GHz
Tx Mode, P
in
=30dBm
V
SS
Terminal, f
in
=0.1~2GHz
Tx Mode, P
in
=30dBm
CTL1, CTL2, CTL3 Terminals
CTL1, CTL2, CTL3 Terminals
CTL1, CTL2, CTL3=V
DD
or CTL1, CTL2, CTL3=0V
CTL1, CTL2, CTL3 Terminals
MIN
2.7
-3.5
-
-0.1
-
-30
2.0
0
-1.3
4
TYP
3.5
-2.5
2.0
-
10
-10
3.0
0
-
-
MAX
5.0
-2.0
5.0
0
30
-
V
DD
0.6
1.3
-
UNITS
V
V
µA
uA
uA
uA
V
V
uA
MΩ
* The voltage of this terminal should be supplied before or same time with other DC supplying
terminals. (CTL1~3, V
SS
).
- 2-
NJG1707PG1
nELECTRICAL
CHARACTRISTICS 2 [Tx Mode]
General Conditions: T
a
=25°C,V
DD
=3.5V,V
SS
=-2.5V, f
in
=885~940MHz
Tested on PCB circuit as shown below.
Insertion loss of each connectors, striplines, and capacitors are excluded.
TX, RX, ANT1, ANT2, EXT1, EXT2: terminated (50Ω)
TER1, TER2: grounded by 10pF capacitor.
PARAMETER
Tx-ANT1 Insertion Loss
Tx-EXT1 Insertion Loss
Tx-Rx Isolation
Tx-ANT1 Isolation
Tx-ANT2 Isolation
Tx-EXT1 Isolation
Tx-EXT2 Isolation
Input Power at
0.5dB Compression 1
Adjacent Channel
Leakage Power 1
Adjacent Channel
Leakage Power 2
2nd Harmonics 1
3rd Harmonics 1
VSWR 1
Switching Time 1
SYMBOL
LOSS1
LOSS2
ISL1
ISL2
ISL3
ISL4
ISL5
P
-0.5dB
(1)
ACP1
P
in
=30dBm
P
in
=30dBm
CONDITION
MIN
-
-
24
22
33
21
32
33
-
TYP MAX UNITS
0.50
0.50
27
25
38
24
37
35
-63
0.65
0.65
-
-
-
-
-
-
-60
dB
dB
dB
dB
dB
dB
dB
dBm
dBc
P
in
=30dBm
Tx-ANT1, Tx-EXT1 passing
P
in
=30dBm
Tx-EXT1 passing
P
in
=30dBm
Tx-ANT1, Tx-EXT1 passing
P
in
=30dBm
Tx-ANT1 passing
P
in
=30dBm
Tx-ANT1,Tx-EXT1 passing
Tx-ANT1,Tx-EXT1 passing
PDC Standard, ±50kHz offset
P
in
=30dBm
Input Signal ACP=-64dBc @ 30dBm
PDC Standard, ±100kHz offset
P
in
=30dBm
Input Signal ACP=-76dBc @ 30dBm
P
in
=30dBm
Input Signal 2nd Harmonics=-70dBc
P
in
=30dBm
Input Signal 3rd Harmonics=-100dBc
ACP2
2f
0
(1)
3f
0
(1)
VSWR1
T
D
1
-
-
-
-
-
-74
-65
-64
1.2
120
-70
-63
-62
1.5
500
dBc
dBc
dBc
Tx-ANT1, Tx-EXT1 passing
CTL1~3
nsec
-3-
NJG1707PG1
nELECTRICAL
CHARACTRISTICS 3 [Rx Mode]
General Conditions: T
a
=25°C, V
DD
=3.5V, V
SS
=0V, f
in
=810~885MHz
Tested on PCB circuit as shown below.
Insertion loss of each connectors, striplines, and capacitors are excluded.
TX, RX, ANT1, ANT2, EXT1, EXT2: terminated (50Ω)
TER1, TER2: grounded by 10pF capacitor.
PARAMETER
Rx-ANT1 Insertion Loss
Rx-ANT2 Insertion Loss
Rx-EXT1 Insertion Loss
Rx-EXT2 Insertion Loss
Rx-ANT1 Isolation
Rx-ANT2 Isolation
Rx-EXT1 Isolation
Rx-EXT2 Isolation
Input Power at 1dB
Compression 1
VSWR 2
Switching Time 2
SYMBOL
LOSS3
LOSS4
LOSS5
LOSS6
ISL6
ISL7
ISL8
ISL9
P
-1dB
(1)
VSWR2
T
D
2
P
in
=10dBm
P
in
=10dBm
P
in
=10dBm
P
in
=10dBm
P
in
=10dBm
Rx-ANT2, Rx-EXT1, Rx-EXT2 passing
CONDITION
MIN
-
-
-
-
22
24
22
22
21
-
-
TYP
0.65
0.60
0.70
0.65
26
30
26
26
26
1.2
120
MAX
0.80
0.75
0.85
0.80
-
-
-
-
-
1.6
500
UNITS
dB
dB
dB
dB
dB
dB
dB
dB
dBm
P
in
=10dBm
Rx-ANT1, Rx-EXT1, Rx-EXT2 passing
P
in
=10dBm
Rx-ANT1, Rx-ANT2, Rx-EXT2 passing
P
in
=10dBm
Rx-ANT1, Rx-ANT2, Rx-EXT1 passing
Rx-ANT1, Rx-ANT2, Rx-EXT1, Rx-
EXT2 passing
RX-ANT1, RX-ANT2, RX-EXT1, RX-
EXT2 passing
CTL1~3
nsec
nELECTRICAL
CHARACTRISTICS 4 [LNA]
General Conditions: T
a
=25°C, V
DD
=3.5V, V
SS
=0V, f
in
=820MHz
Tested on PCB circuit as shown below.
PARAMETER
Operation Frequency
Drain Voltage
Current Consumption
Small Signal Gain
Gain Flatness
Noise Figure
Pout at 1dB Gain
Compression Point
Input 3
rd
order
Intercept Point
LNAIN Port VSWR
LNAOUT Port VSWR
SYMBOL
f
RF
V
DD
3
I
DD
3
Gain
G
flat
NF
P
-1dB
(2)
IIP3
VSWR
i
VSWR
o
fRF=810~885MHz
No RF input
CONDITION
MIN
810
2.5
-
16.0
-
-
-3.0
-8.0
-
-
TYP
-
2.7
2.7
17.5
0.5
1.4
+1.0
-4.5
1.5
1.5
MAX
885
4.5
3.6
18.5
1.0
1.6
-
-
2.5
2.5
UNITS
MHz
V
mA
dB
dB
dB
dBm
dBm
- 4-
NJG1707PG1
nTERMINAL
INFORMATION
PIN NO.
4
5
6
7
SYMBOL
CTL1
CTL2
CTL3
V
SS
DESCRIPTIONS
Control signal input terminal of high impedance C-MOS logic. Logic level: High; more
than +2V, Low; 0~+0.6V. Please connect to GND or V
DD
with 100kΩ if potential is
open or uncertain.
Negative supply terminal. Negative voltage of -3.5~-2.0V must be supplied on Tx
mode. This terminal is isolated on Rx mode, so open or –2.5~0V condition can be
used. Please connect bypass capacitor with GND to keep RF performance.
Positive supply terminal. The voltage of this terminal should be supplied before or
same time with other DC supplying terminals (CTL1~3, V
SS
). The bias voltage should
be +2.7~+5.0V. Please connect bypass capacitor with GND to keep RF performance.
RF port for Rx signal. A DC cut capacitor (56pF~100pF) is required to block V
DD
voltage.
RF port for Tx/Rx signal. A DC cut capacitor (56pF~100pF) is required to block V
DD
voltage.
Tx power input terminal. A DC cut capacitor is required to block V
DD
voltage, and also
an external matching circuit is required to improve VSWR(See Application circuit).
A termination terminal for ANT1 in case ANT2 is in use. The influence of ANT1
against ANT2 is reduced. A DC cut capacitor (10pF) is required to block V
DD
voltage.
RF port for Tx/Rx signal. A DC cut capacitor (56pF~100pF) is required to block V
DD
voltage.
Rx output terminal. A DC cut capacitor is required to block V
DD
voltage, and also an
external matching circuit is required to improve VSWR(See Application circuit).
RF port for Rx signal. A DC cut capacitor (56pF~100pF) is required to block V
DD
voltage.
A termination terminal for ANT2 in case ANT1 is in use. The influence of ANT2
against ANT1 is reduced. A DC cut capacitor (10pF) is required to block V
DD
voltage.
Ground terminal of LNA. Please place ground plane close to this pin for good RF
performance.
LNA input terminal. An external matching circuit is required.
LNA output terminal. An external matching circuit with LNA biasing element L3, L4 as
in application circuit is required.
Bypass capacitor terminal of LNA. Please place C9 as in application circuit close to
this terminal.
Ground terminal. Please connect to ground plane as close as possible for good RF
performance.
9
11
13
15
17
19
21
23
25
26,27
28
30
31
1,2,3,8,10,
12,14,16,1
8,20,22,24,
29,32
V
DD
EXT2
EXT1
TX
TER2
ANT1
RX
ANT2
TER1
GND(LNA)
LNAIN
LNAOUT
EXTCAP
GND
nTRUTH
TABLE
”H”=V
CTL (H)
, ”L”=V
CTL (L)
, ”X”=H or L
CONTROL INPUT
ROUTE
Tx-ANT1
Tx-EXT1
Rx-ANT1
Rx-ANT2
Rx-EXT1
Rx-EXT2
Tx/Rx
CTL1
H
H
L
L
L
L
Diversity IN/OUT
CTL2
X
X
L
H
L
H
CTL3
H
L
H
H
L
L
CONTROL OUTPUT
SW1 SW2 SW3 SW4 SW5 SW6 SW7 SW8 SW9
OFF OFF OFF
OFF OFF
OFF OFF
ON
OFF
ON
ON
ON
OFF
OFF
ON
ON
ON
ON
ON
ON
OFF OFF OFF
ON
OFF
ON
ON
ON
ON
ON
ON
OFF
ON
ON
ON
ON
ON
ON
ON
ON
OFF
ON
OFF OFF
OFF OFF OFF OFF
ON
OFF OFF
OFF OFF OFF
-5-
工业自动化与控制
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
