NJU3152
PRELIMINARY
4-BIT SINGLE CHIP OTP TINY CONTROLLER
s
GENERAL DESCRIPTION
The
NJU3152
is the C-MOS 4-bit Single Chip OTP type
Micro Controller with programmable Flash Memory.
It is completely compatible with the
NJU3102
in function
and the pin configuration. Therefore, the
NJU3152
is
suitable for the final evaluation before
NJU3102
mask
generation, the small quantity production and short lead-
time.
*
In this data sheet, only OTP programming and the
difference between
NJU3152
and
NJU3102
are
mentioned mainly.
Therefore the detail function and specification should
be referred on the
NJU3102
data sheet.
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PACKAGE OUTLINE
NJU3152L
NJU3152G
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FEATURES
q
q
q
q
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Internal One Time Programmable ROM 1,024 X 8bits
Internal Data RAM
32 X 4bits
Wide operating voltage range
2.7V ~ 5.5V
Package outline
SDIP22 / SOP22
ROM programmer “SUPERPRO/L” by XELTEK co,.
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PIN CONFIGURATION IN OTP PROGRAMMING MODE
Open
D0
D1
D2
Open
D3
Open
PROM
CLK
REQ
V
SS
1
2
3
4
5
6
7
8
9
10
11
22
21
20
19
18
17
16
15
14
13
12
V
DD
Open
CNT2
CNT1
D7
Open
D6
D5
D4
RESET
Note) The pin configuration in Normal operating mode is the same as
NJU3102.
-1-
NJU3152
s
BLOCK DIAGRAM
CPU CORE
STACK
TLUaddr
MUX
OTP ROM
1024 x 8 bit
IR
RAM
32 x 4 bit
ID
STANDBY
CONTROLLER
ALU
CPU
TIMING
GENERATOR
OSC
TEST
RESET
OSC1
OSC2
PC
X’-Reg
Y’-Reg
X-Reg
Y-Reg
AC
V
DD
V
SS
PORT_A
PORT_B
PORT_E
PORT_D
PORT_C
PD0
PD1
PD2
PD3
PC0
-2-
PC1
PB0
PB1
PB2
PB3
PE0
PE1
PA0
PA1
PA2
PA3
NJU3152
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TERMINAL DESCRIPTION IN OTP PROGRAMMING MODE
No.
12
2 - 4,
6,
13 - 15,
18
19,
20
10
9
8
22
11
Note 1)
2)
SYMBOL
RESET
INPUT/OUTPUT
INPUT
FUNCTION
RESET terminal.
When the low-level input-signal, the system is initialized.
D0 - D7
CNT1
CNT2
REQ
CLK
PROM
V
DD
V
SS
INPUT/OUTPUT Data bus
INPUT
INPUT
OUTPUT
INPUT
INPUT
-
-
OTP control input terminal
Request output terminal
Clock input terminal
OTP programming enable terminal
Power Source (5V)
Power Source (0V)
Use at V
DD
=5V in OTP programming mode.
Non connect anything to the other terminals.
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Difference between NJU3152 (OTP version) and NJU3102 (MASK version)
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Operating mode
NJU3152
has two operating modes. One is ”Normal operating mode” and the other is “OTP programming
mode”.
•
Normal operating mode
The ”TEST” terminal is set to low level. (The terminal is recommended to connect to GND.)
Operating voltage range; 2.7V ~ 5.5V.
OTP Programming mode
User program is read out from or written into the OTP by the universal programmer “SUPERPRO/L” and
converting adapter made by XELTEK co,.(USA).
•
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Option information set in the initialization
When the initialization is performed(RESET terminal is “L”), the operation information stored in option area is
set as shown in the following timing chart . The option information is set in the term of
1 / f
OSC
x 256clock
after
RESET releasing and oscillation stability time. After information set, the program counter is set to 0000H and
the
NJU3152
operates in normal.
[ TIMING CHART ]
Oscillation
Stability
Time
Oscillator
Clock
Option information setting
1/f
OSC
x256clock
Normal
Operation
Oscillation
Start
PC=0000H
RESET
f
OSC
=4MHz
about 64
µ
sec
-3-
NJU3152
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ABSOLUTE MAXIMUM RATINGS
(Ta=25°C)
PARAMETER
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Storage Temperature
SYMBOL
V
DD
V
IN
V
OUT
T
opr
T
stg
RATINGS
-0.3 ~ +7.0
-0.3 ~ V
DD
+ 0.3
-0.3 ~ V
DD
+ 0.3
-20 ~ +75
-55 ~ +125
UNIT
V
V
V
°C
°C
Note)
The difference of electrical characteristics between
NJU3152
(OTP version) and
NJU3102
(MASK version)
NJU3102
•
NJU3152
→
→
→
→
→
→
→
2.7V
Supply Voltage (V
DD
) MIN.
Supply Current
5V (I
DD1
) Max.
(I
DD2
) Max.
(I
DD3
) Max.
(I
DD4
) Max.
3V (I
DD1
) Max.
(I
DD2
) Max.
(I
DD3
) Max.
(I
DD4
) Max.
2.4V
•
4.5mA
4.5mA
4.3mA
5.0
µ
A
2.3mA
2.3mA
2.1mA
3.0
µ
A
30mA
30mA
30mA
20
µ
A
20mA
20mA
20mA
20
µ
A
-4-
NJU3152
s
ELECTRICAL CHARACTERISTICS
SYM
BOL
V
DD
I
DD1
DC CHARACTERISTICS 1
(V
DD
=3.6~5.5V, V
SS
=0V, Ta=-20~75°C)
NOT
MIN
TYP
MAX
UNIT
E
3.6
5.5
V
30
mA
*3
PARAMETER
Supply Voltage
CONDITIONS
V
DD
V
DD
V
DD
=5V, f
OSC
=2MHz
X’tal Oscillation in Reset
V
DD
V
DD
=5V, f
OSC
=2MHz
Ceramic Oscillation in Reset
V
DD
V
DD
=5V, f
OSC
=2MHz
CR Oscillation in Reset
V
DD
V
DD
=5V, STANDBY Mode
V
DD
V
DD
=5V, f
OSC
=4MHz, Operating
PA0~PA3, PB0~PB3, PC0, PC1,
PD0~PD3
PE0, PE1, RESET
OSC1
PA0~PA3, PB0~PB3, PC0, PC1,
PD0~PD3
PE0, PE1, RESET
OSC1
V
DD
=5.5V, V
IN
=5.5V
PA0~PA3, PB0~PB3, PC0, PC1,
PD0~PD3, PE0, PE1, RESET
V
DD
=5.5V, V
IN
=0V
Without pull-up resistance
PA0~PA3, PB0~PB3, PC0, PC1,
PD0~PD3, PE0, PE1, RESET
V
DD
=5.5V, V
IN
=0V
With pull-up resistance
PA0~PA3, PB0~PB3, PC0, PC1,
PD0~PD3, PE0, PE1
I
OH
=-100µA
PA0~PA3, PB0~PB3, PC0, PC1,
PD0~PD3, PE0, PE1
I
OL1
=400µA
PA0~PA3, PB0~PB3, PC0, PC1,
PE0, PE1
I
OL2
=15mA
PD0~PD3
V
DD
=5.5V, V
OH
=5.5V
PD0~PD3
I
DD2
Supply Current
I
DD3
I
DD4
I
DD5
High-Level
Input Voltage
V
IH1
V
IH2
V
IH3
V
IL1
V
IL2
V
IL3
I
IH
30
mA
*3
30
20
30
0.7V
DD
0.8V
DD
V
DD
-1.0
0
0
0
V
DD
V
DD
V
DD
0.3V
DD
0.2V
DD
1.0
10
mA
µA
mA
V
V
V
V
V
V
µA
*3
*3
*3
*1
*1
*1
*1
Low-level
Input Voltage
High-Level
Input Current
*1
I
IL1
Low-Level
Input Current
I
IL2
-10
µA
*1
-100
µA
*1
High-Level
Output Voltage
V
OH
V
DD
-0.5
V
*2
Low-Level
Output Voltage
Output
Leakage
Current
V
OL1
V
OL2
I
OD
0.5
2.0
10
V
V
µA
pF
*2
*2
*2
Except V
DD
, V
SS
terminals
Input Capacitance C
IN
f
OSC
=1MHz
Other terminals : 0V
*1 Input/output port is set as an Input terminal.
*2 Input/output port is set as an Output terminal.
*3 Except the current through Pull-up resister.
10
20
-5-
FPGA/CPLD
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