NJU3426
PRELIMINARY
16-SEGMENT X 15-Digit
VFD CONTROLLER / DRIVER
!
GENERAL DESCRIPTION
The
NJU3426
is a VFD (Vacuum Fluorescent Display)
controller/driver to dynamically drive up to 16 segments x 15
digits. It consists of display data RAM, an address counter,
command registers, a serial interface and high voltage drivers.
The direct control from the MPU and high voltage drivers of
45V make the
NJU3426
well suited for various VFD displays.
!
PACKAGE OUTLINE
NJU3426FP1
!
FEATURES
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Directly Drives 16-segment x 15-digit
High VFD Driving Voltage
: |V
DD
-V
FDP
|=45V
Display Shift Function
Programmable Duty Ratio for Timing Signal
:2/16, 4/16, 6/16, 8/16, 10/16, 12/16, 14/16, 15/16 duty
Display ON/OFF Control Function
Display Data RAM
: 30 x 8-bit
Built-in Oscillator (Formed by Connecting an External Ceramic Resonator)
8-bit Serial Interface
Power-ON Reset Function
Operating Voltage
:3.0 to 5.5V
C-MOS Technology
Package Outline
:QFP48-P1
S
0
to S
15
T
0
to T
13
!
BLOCK DIAGRAM
V
DD
V
SS
V
FDP
High Voltage Driver
High Voltage Driver
Segment Data Latch
Timing Counter
Character
Address Counter
Address Counter
Display RAM
30 x8-bit
Initial Character
Address Counter
Duty
Counter
Timing
Counter
OSC
Instruction Decoder
XT
XTb
SI
SCK
CSb
Serial Buffer
REST
RSTb
02/08/29
-1-
NJU3426
!
FUNCTION DESCRIPTION
(1) ADDRESS COUNTER
The address counter indicates the “Display data RAM address”, in which the display data will be transferred and stored.
For the data transmission, once an initial RAM address is determined, the display data can be continuously transmitted
without setting the RAM address each time. When the upper 2 bits (B7 and B6) of the 1st word are “0,0”, the lower 5
bits (B4 to B0) are recognized as RAM address data. And, the 2nd word is recognized as display data, which will be
stored in the RAM address designated by the 1st word, and simultaneously the RAM address is counted up by an
auto-increment operation.
The “Display data RAM address”, which can be specified by the 1
st
word, ranges from “0,0,0,0,0” (00
H
) to “1,1,1,0,1”
(1D
H
). However, the auto-increment keeps counting up to “1,1,1,1,1” (1F
H
) every display data transmission because of
the 5-bit address counter, and finally the RAM address wraps to “0,0,0,0,0” (00
H
) and begins counting up. Note that the
display data, stored in the RAM address of “1,1,1,1,0” (1E
H
) and “1,1,1,1,1” (1F
H
), is ignored in this sequence.
DISPLAY DATA RAM ADDRESS
B7
0
B6
0
B5
*
B4
AD4
B3
AD3
B2
AD2
B1
AD1
B0
AD0
Recognition data
Display data RAM address
*:don’t care
Character
address
B7
B6
B5
B4
B3
B2
B1
B0
RAM
Address
B7
B6
B5
B4
B3
B2
B1
B0
RAM
Address
T
0
T
1
T
2
T
3
T
4
T
5
T
6
T
7
T
8
T
9
T
10
T
11
T
12
T
13
C
0
C
1
C
2
C
3
C
4
C
5
C
6
C
7
C
8
C
9
C
10
C
11
C
12
C
13
C
14
S
15
S
14
S
13
S
12
S
11
S
10
S
9
S
8
01
H
03
H
05
H
07
H
09
H
0B
H
0D
H
0F
H
11
H
13
H
15
H
17
H
19
H
1B
H
1D
H
1F
H
S
7
S
6
S
5
S
4
S
3
S
2
S
1
S
0
00
H
02
H
04
H
06
H
08
H
0A
H
0C
H
0E
H
10
H
12
H
14
H
16
H
18
H
1A
H
1C
H
1E
H
: These display data is ignored.
DISPLAY DATA RAM MAPPING
-2-
NJU3426
(2) COMMAND REGISTER 1
The “Command register 1” is used for setting “Duty ratio for timing signal”, “Display control ON/OFF” and “Shifting
display digits”. When the upper 1 bit (B7) of the 1
st
word is “1”, the lower 7 bits (B6 to B0) are recognized as
command data, and stored in the “Command register 1”. Note that changing the “Duty ratio” or “Shifting display
digits” must be executed under the “Display control OFF”, otherwise it may cause flickering. The contents of the
“Command register 1” is initially set up at power-ON reset or reset signal, as shown below.
DEFAULT VALUES OF COMMAND REGISTER 1
•
Duty ratio for timing signal
: 2/16
•
Display control ON/OFF
: OFF
•
Shifting display digits
:7
B7
1
B6
DT2
B5
DT1
B4
DT0
B3
DSP
B2
DE2
B1
DE1
B0
DE0
Recognition data
Duty ratio for
timing signal
Display control
ON / OFF
Shifting display digits
MD2
0
0
0
0
1
1
1
1
MD1
0
0
1
1
0
0
1
1
MD0
0
1
0
1
0
1
0
1
Duty ratio for timing signal
2/16
4/16
6/16
8/16
10/16
12/16
14/16
15/16
Note.)
DSP
Display control
0
OFF
1
ON
When the “Display control is OFF” is set, all output pins become in display OFF state.
DE2
0
0
0
0
1
1
1
1
DE1
0
0
1
1
0
0
1
1
DE0
0
1
0
1
0
1
0
1
Shifting display digits
7
8
9
10
11
12
13
14
-3-
NJU3426
(3) COMMAND REGISTER 2
The “Command register 2” is used for setting the “Initial character address” , which corresponds to the T
0
pin. When the
upper 2 bits (B7 and B6) of the 1
st
word is “0,1”, the lower 4 bits (B3 to B0) are recognized as command data, and stored
in the “Command register 2”. The contents of the “Command register 2” is initially set up at power-ON reset or reset
signal, as shown below.
DEFAULT VALUES OF COMMAND REGISTER 2
•
Initial character address : C1 (0,0,0,1)
B7
0
B6
1
B5
*
B4
*
B3
DS3
B2
DS2
B1
DS1
B0
DS0
Recognition data
Initial character address
*:don’t care
DS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
DS2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
DS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
DS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Initial character address
C
0
C
1
C
2
C
3
C
4
C
5
C
6
C
7
C
8
C
9
C
10
C
11
C
12
C
13
C
14
Prohibited
-4-
NJU3426
(4) DISPLAY SHIFT OPERATION
The display shift operation can be performed by changing the “Initial character address” of the “Command register 2”.
And, the number of digits for the display shift in the loop is determined by the “Shifting display digits” of the
“Command register 1”. In other words, shifting display area ranges from the “Initial character address” specified by the
“Command register 2” to the last address designated by the “Command register 1”.
The default value of the “Initial character address” is C
1
(0,0,0,1), as shown in the table of “Display data RAM”. In
addition, supposing that the value of the “Shifting display digits” is “N”, the “Initial character address” must be set in the
range between C
0
and C
N
in order not to exceed the digit “N”. Because the display shift operation doesn’t apply to the
addresses beyond the range of the digit “N”, the display images, initially set, appear on these addresses. Just for
reference, one character of display image is composed of 16 segments.
HOW TO SET LEFT DISPLAY SHIFT
The left display shift is carried out by incrementing the “Initial character address” gradually like C
2
, C
3
, C
4
, ---
C
N
. To the contrary, decrementing the address performs right display shift. The following description
provides the example on how to set the left display shift, using alphanumeric display images such as “0”, “1”,
“2”, ---, “9”, “A”, “B”, ---, and “E”.
STEP1) Setting display images in the display data RAM
•
Display RAM data
Character address
Display image
C
0
0
C
1
1
C
2
2
C
3
3
C
4
4
C
5
5
C
6
6
C
7
7
C
8
8
C
9
C
10
C
11
C
12
C
13
C
14
9
A
B
C
D
E
SETP2) Setting the
“Initial
character address” to C
2
and the
“Shifting
display digits N” to 12 (T
11
).
Shifting display digits
Character
address
Timing output
terminals
Character
Display image
C
1
C
2
C
3
C
12
C
0
C
13
C
14
T
0
1
T
1
2
T
10
11
T
11
12
T
12
13
T
13
14
is not shifted.
In this setting, the display images of "2", "3”,- - - appear on the T
0
, T
1
, T
2
, - - - T
10
pins respectively, and the
image “0” is on the T
11
pin, which is assigned to the 12
th
character address. The display images “D” and “E”
don’t shift but remain on the T
12
and T
13
pins, assigned to the 13
th
and 14
th
characters respectively, because their
character addresses are outside of the digit “N”.
STEP3) Changing the
“Initial
character address” to C
3
, and leaving the
“Shifting
display digits N” as 12 (T
11
).
Shifting display digits
Character
address
Timing output
terminals
Character
Display image
C
2
C
3
C
4
C
0
C
1
C
13
C
14
T
0
1
T
1
2
T
10
11
T
11
12
T
12
13
T
13
14
is not shifted.
-5-
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