NJU39610
MICROSTEPPING MOTOR CONTROLLER WITH DUAL DAC
s
GENERAL DESCRIPTION
NJU39610 is a dual 7-bit+sign, Digital-to-Analog Converter
(DAC) especially developed to be used together with the
NJM3771, Precision Stepper Motor driver in micro-stepping
applications. The NJU39610 has a set of input registers
connected to an 8-bit data port for easy interfacing directly to
a microprocessor. The NJU39610 is well suited for high-
speed micro-stepping application.
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PACKAGE OUTLINE
NJU39610D2
NJU39610FM2
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FEATURES
• Analog control voltages from 3 V down to 0.0 V
• High-speed microprocessor interface
• Automatic fast/slow current decay control
• Full-scale error
• Fast conversion speed
• Matches NJM3771
• Packages
DIP22/PLCC28
±1
LSB
3
µs
s
BLOCK DIAGRAM
V
DD
V
Ref
NJU39610
WR
C
D
E1
CS
C
D
R
Level 2
DA- Data 1
E
E1
C
D
R
Sign 1
R
Level 1
Digit
Comp
E
CD 1
DA 1
E
E2
A0
E3
C
D
A1
E4
D7 - D0
C
D
R
R
DA- Data 2
D/A
E
D/A
Digit
Comp
E4
C
D
R
DA
E
2
CD 2
E
Sign 2
POR
RESET
R
V
ss
Figure 1. Block Diagram
NJU39610
s
PIN CONFIGURATIONS
Sign
2
CD
2
V
SS
N/C
26
CS
V
ref
DA
1
Sign
1
CD
1
V
DD
WR
D7
D6
D5
D4
D3
1
2
3
4
5
6
7
8
9
10
11
22
21
20
19
Reset
DA
2
Sign
2
CD
2
V
SS
CS
A1
A0
D0
N/C
DA
2
Reset
N/C
V
ref
DA
1
5
6
7
8
9
10
11
28
A1
27
4
3
2
1
A0
25
24
D0
D1
D2
N/C
D3
D4
D5
NJU
39610D2
18
17
16
15
14
13
12
NJU
39610FM2
23
22
21
20
19
N/C
12
CD
1
13
14
15
16
17
Sign
1
V
DD
D2
Figure 2. Pin configurations
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PIN DESCRIPTION
Refer to figure 2.
DIP
PLCC
Symbol
Description
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
9
10
12
13
14
15
16
17
19
20
21
23
24
25
27
28
1
2
3
4
6
7
5
8
11
18
22
26
V
Ref
DA
1
Sign
1
CD
1
V
DD
WR
D7
D6
D5
D4
D3
D2
D1
D0
A0
A1
CS
V
SS
CD
2
Sign
2
DA
2
Reset
Voltage reference supply pin, 2.5 V nominal (3.0 V maximum)
Digital-to-Analog 1, voltage output. Output between 0.0 V and V
R
- 1 LSB.
Sign 1, TTL/CMOS level. To be connected directly to NJM3771 Phase input.
Databit D7 is transfered non inverted from NJU39610 data input.
Current Decay 1, TTL/CMOS level. The signal is automatically generated when
decay level is programmed. LOW level = fast current decay.
Voltage Drain-Drain, logic supply voltage. Normally +5 V.
Write, TTL/CMOS level, input for writing to internal registers.
Data is clocked into flip flops on positive edge.
Data 7, TTL/CMOS level, input to set data bit 7 in data word.
Data 6, TTL/CMOS level, input to set data bit 6 in data word.
Data 5, TTL/CMOS level, input to set data bit 5 in data word.
Data 4, TTL/CMOS level, input to set data bit 4 in data word.
Data 3, TTL/CMOS level, input to set data bit 3 in data word.
Data 2, TTL/CMOS level, input to set data bit 2 in data word.
Data 1, TTL/CMOS level, input to set data bit 1 in data word.
Data 0, TTL/CMOS level, input to set data bit 0 in data word.
Address 0, TTL/CMOS level, input to select data transfer,
A0 selects between cannel 1 (A0 = LOW) and channel 2 (A0 = HIGH).
Address 1, TTL/CMOS level, input to select data transfer. A1 selects between normal
D/A register programming (A1 = LOW) and decay level register programming (A1 = HIGH).
Chip Select, TTL/CMOS level, input to select chip and activate data transfer
from data inputs. LOW level = chip is selected.
Voltage Source-Source. Ground pin, 0 V reference for all signals and
measurements unless otherwise noted.
Current Decay 2, TTL/CMOS level. The signal is automatically generated
when decay level is programmed. LOW level = fast current decay .
Sign 2. TTL/CMOS level. To be connected directly to NJM3771 sign input.
Data bit D7 is transfered non-inverted from NJU39610 data input.
Digital-to-Analog 2, voltage output. Output between 0.0 V and V
ref
- 1 LSB.
Reset, digital input resetting internal registers.
HIGH level = Reset, V
Res
≥
3.5 V = HIGH level. Pulled low internally.
Not Connected
N/C
WR
N/C
D7
D6
D1
18
NJU39610
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DEFINITION OF TERMS
Resolution
Resolution is defined as the reciprocal of the number of discrete steps in the DAC output. It is directly related to the
number of switches or bits within the DAC. For example, NJU39610 has 2
7
, or 128, output levels and therefor has 7
bits resolution. Remember that this is not equal to the number of microsteps available.
Linearity Error
Linearity error is the maximum deviation from a straight line passing through the end points of the DAC transfer
characteristic. It is measured after adjusting for zero and full scale. Linearity error is a parameter intrinsic to the
device and cannot be externally adjusted.
Power Supply Sensitivity
Power supply sensitivity is a measure of the effect of power supply changes on the DAC full-scale output
Settling Time
Full-scale current settling time requires zero-to-full-scale or full-scale-to-zero output change. Settling time is the
time required from a code transition until the DAC output reaches within
±
1
/
2
LSB of the final output value.
Full-scale ErrorFull-scale error is a measure of the output error between an ideal DAC and the actual device output.
Differential Non-linearity
The difference between any two consecutive codes in the transfer curve from the theoretical 1LSB, is differential
non-linearity
Monotonic
If the output of a DAC increases for increasing digital input code, then the DAC is monotonic. A 7-bit DAC which is
monotonic to 7 bits simply means that increasing digital input codes will produce an increasing analog output.
NJU39610 is monotonic to 7 bits.
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FUNCTIONAL DESCRIPTION
Each DAC channel contains two registers, a digital comparator, a flip flop, and a D/A converter. A block diagram is
shown on the first page. One of the registers stores the current level, below which, fast current decay is initiated.
The status of the CD outputs determines a fast or slow current decay to be used in the driver.
The digital comparator compares each new value with the previous one and the value for the preset level for fast
current decay. If the new value is strictly lower than both of the others, a fast current decay condition exists. The flip
flop sets the CD output. The CD output is updated each time a new value is loaded into the D/A register. The fast
current decay signals are used by the driver circuit, NJM3771, to change the current control scheme of the output
stages. This is to avoid motor current dragging which occurs at high stepping rates and during the negative current
slopes, as illustrated in figure 9. Eight different levels for initiation of fast current decay can be selected.
The sign outputs generate the phase shifts, i.e., they reverse the current direction in the phase windings.
Output
Output
Output
Actual
Gain
error
Correct
Endpoint
non-linearity
More
than 2
bits
Less
than 2
bits
Negative
difference
Positive
difference
Offset error
Full scale
Input
Input
Input
Figure 5. Errors in D/A conversion.
Figure 4. Errors in D/A conversion.
Figure 3. Errors in D/A conversion.
Differential non-linearity of more than Differential non-linearity of less than 1 Non-linearity, gain and offset errors.
bit, output is monotonic.
1 bit, output is non-monotonic.
NJU39610
Data Bus Interface
NJU39610 is designed to be compatible with 8-bit microprocessors such as the 6800, 6801, 6803, 6808, 6809,
8051, 8085, Z80 and other popular types and their 16/32 bit counter parts in 8 bit data mode. The data bus inter-
face consists of 8 data bits, write signal, chip select, and two address pins. All inputs are TTL-compatible (except
reset). The two address pins control data transfer to the four internal D-type registers. Data is transferred according
to figure 10 and on the positive edge of the write signal.
Current Direction, Sign
1
& Sign
2
These bits are transferred from D
7
when writing in the respective DA register. A
0
and A
1
must be set according to
the data transfer table in figure 10.
Current Decay, CD
1
& CD
2
CD
1
and CD
2
are two active low signals (LOW = fast current decay). CD
1
is active if the previous value of DA-Data1
is strictly larger than the new value of DA-Data1 and the value of the level register LEVEL1 (L
61
… L
41
) is strictly
larger than the new value of DA-Data1. CD
1
is updated every time a new value is loaded into DA-Data1.
The logic definition of CD
1
is:
CD
1
= NOT{[(D
6
… D
0
) < (Q
61
… Q
01
)] AND[(D
6
…D
4
) < (L
61
… L
41
)]}
Where (D
6
… D
0
) is the new value being sent to DA-Data1 and (Q
61
… Q
01
) is DA-Data1’s old value. (L
61
… L
41
) are
the three bits for setting the current decay level at LEVEL1.
The logic definition of CD
2
is analog to CD
1
:
CD
2
= NOT{[(D
6
… D
0
) < (Q
62
… Q
02
)] AND[(D
6
…D
4
) < (L
62
… L
42
)]}
Where (L
62
… L
42
) is the level programmed in channel 2’s level register. (D
6
… D
0
) and (Q
62
… Q
02
) are the new and
old values of DA-Data2.
The two level registers, LEVEL1 and LEVEL2, consist of three flip flops each and they are compared against the
three most significant bits of the DA-Data value, sign bit excluded.
I
2
[mA]
T max
T
2
[mNm]
DA output [V]
Current dragging
Tnom
Tmin
I
CD
t
T
1
[mNm]
I
1
[mA]
Time
Figure 6a. Assuming that torque is
proportional to the current in resp.
winding it is possible to draw figure
8b.
Figure 6b. An example of accessible
positions with a given torque devia-
tion/fullstep. Note that 1:st
µstep
sets highest resolution. Data points
are exaggerated for illustration
purpose.
TNom = code 127.
Figure 7. Motor current dragging at
high step rates and current decay
influence. Fast current decay will
make it possible for the current to
follow the ideal sine curve. Output
shown without sign shift.
CS
0
0
0
0
1
A0
0
0
1
1
X
A1
0
1
0
1
X
Data Transfer
D7 —> Sign1, (D6—D0) —> (Q61—Q01), New value —> CD1
(D6—D4) —> (L61—L41)
D7 —> Sign2, (D6—D0) —> (Q62—Q02), New value —> CD2
(D6—D4) —> (L62—L42)
No Transfer
Figure 8. Table showing how data is transfered inside NJU39610.
NJU39610
DA
1
and DA
2
These are the two outputs of DAC1 and DAC2. Input to the DACs are internal data bus (Q
61
… Q
01
) and (Q
62
…
Q
02
).
Reference Voltage V
Ref
V
Ref
is the analog input for the two DACs. Special care in layout, gives a very low voltage drop from pin to resistor.
Any V
Ref
between 0.0 V and V
DD
can be applied, but output might be non-linear above 3.0 V.
Power-on Reset
This function automatically resets all internal flip flops at power-on. This results in V
SS
voltage at both DAC outputs
and all digital outputs.
Reset
If Reset is not used, leave it disconnected. Reset can be used to measure leakage currents from V
DD
.
Time when motor is in
a compromise
position.
Time when micro
position is correct.
Write
signal.
Motor
position.
Writing to
channel 1.
Writing to
channel 2.
Time
Ideal data = desired position
Write time = incorrect position
Useful time = correct
position
Double pulse write signal
Actual data = true position
Normal resolution
Figure 9. Double pulse programming, in- and output signals.
Time when motor is in
an intermediate
position.
Time when micro
position is almost
correct.
Write
signal.
Motor position. Note
that position is always
a compromise.
Writing to
channel 1.
Writing to
channel 2.
Time
Useful time = compromise position
with equally spaced angles
Useful time = almost
correct position
Single pulse write signal
"Ideal data" = desired
position
Actual data = true position
Note increased resolution
Figure 10. Single pulse programming, in- and output signals.
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